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A datasheet quotes an interrupt latency of 12 cycles on a 48 MHz core. In time that is

  • A.576 ns
  • B.250 ns
  • C.12 ns
  • D.4 \( \mu \)s

Answer: B

Twelve cycles at 48 MHz is 12 divided by 48 million, that is a quarter of a microsecond. Whether that is acceptable depends entirely on the deadline: it is generous for a keypad and far too slow for a switching converter's current loop.

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