Discussion
................... are employed to specify parameters that can be supplied to VHDL entities.
Answer: D
Parameters supplied to VHDL entities are specified by generics.
A generic clause in an entity declaration defines constants, such as a bus width or a delay, whose values can be set when the entity is instantiated with a generic map. This lets one design, for example an N-bit adder, be reused with different sizes.
Ports define the signals flowing in and out of the entity, not its parameters; 'port numbers' is not a VHDL construct. Packages hold shared declarations such as types, constants and functions for many design units. Declarations is a general term, not the mechanism for parameterising an entity.
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