Logic Gates Questions and Answers

Answer: C

Correct answer: logic analyzer

A logic analyzer captures many digital lines at once and displays them as a timing diagram, which is what allows the actual waveforms to be compared with the expected ones. A DMM reads a single value and a spectrum analyzer works in the frequency domain.

Answer: A

Correct answer: Y = A + B + C + D

OR is written with plus signs. The dot form would give AND, and the other two symbols are not Boolean operators.

Answer: D

Correct answer: FOR

The three basic Boolean operations are AND, OR and NOT; every other function can be built from them. FOR is a programming keyword, not a logical operation.

Answer: A

Correct answer: True

CMOS draws current essentially only while switching, so its static power dissipation is negligible - far lower than TTL or ECL, which draw current continuously.

Answer: A

Correct answer: True

A Johnson counter is a shift register with inverted feedback, and its stages produce a set of repetitive waveforms offset in phase, which is what makes it a standard waveform generator.

Answer: C

Correct answer: AND-OR

A multiplexer forms the AND of each data input with its decoded select condition, and then ORs the results together, so exactly one input reaches the output. That two-level AND-OR structure is the standard implementation.

Answer: A

Correct answer: True

Either gate can gate a waveform, depending on the level held on the control input: an AND passes the signal when its other input is HIGH and blocks it at 0 when LOW, and an OR passes it when its other input is LOW and blocks it at 1 when HIGH.

Answer: C

Correct answer: 3

The 7411 is a triple three-input AND gate: three gates, each with three inputs, using twelve of the fourteen pins.

Answer: C

Correct answer: enable or disable, enable or disable

Both gates can do either, depending on the level held on the control input. Holding one AND input HIGH passes the signal and holding it LOW blocks it at 0; holding one OR input LOW passes the signal and holding it HIGH blocks it at 1.

Answer: C

Correct answer: 4

Write \( F=(x'+y')(z+w) \) and let \( A = x\,\text{NAND}\,y = x'+y' \). Then

\[ F = A(z+w) = Az + Aw = \big((Az)'\cdot(Aw)'\big)' \]

so \( (Az)' \) and \( (Aw)' \) are two more NAND gates and a fourth NAND combines them. Four gates in all: \( \text{NAND}(x,y) \), \( \text{NAND}(A,z) \), \( \text{NAND}(A,w) \) and \( \text{NAND} \) of the last two.