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Memory Management Questions and Answers

51.

In paging the user provides only ________ which is partitioned by the hardware into ________ and ______

Answer: A

Correct answer: one address, page number, offset

In paging the programmer sees a single linear address; it is the hardware that splits it into a page number and an offset. In segmentation the two parts are supplied separately, which is the difference between the two schemes.

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Answer: B

Correct answer: between 0 and segment limit

An offset is a distance from the start of the segment, so it is legal from 0 up to but not including the limit. Anything else refers outside the segment and is trapped.

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Answer: A

Correct answer: it is added to the segment base to produce the physical memory address

The logical address is a pair: the segment number selects the entry and the offset says how far into the segment. The physical address is therefore

\[ \text{physical} = \text{base} + d \]

An offset used as a physical address on its own would ignore where the segment actually sits in memory.

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57.

When the entries in the segment tables of two different processes point to the same physical location :

Answer: C

Correct answer: segments are shared

If two processes' segment table entries give the same base and limit, both are using the same physical memory, which is how code is shared between processes. Segmentation makes this natural because a segment is a logical unit such as a library.

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59.

If there are 32 segments, each of size 1Kb, then the logical address should have :

Answer: A

Correct answer: 15 bits

Selecting one of 32 segments needs \( \log_{2}32 = 5 \) bits, and an offset within a 1 KB segment needs \( \log_{2}1024 = 10 \) bits:

\[ 5 + 10 = 15\ \text{bits} \]

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60.

Consider a computer with 8 Mbytes of main memory and a 128 K cache. The cache block size is 4 K. It uses a direct mapping scheme for cache management. How many different main memory blocks can map onto a given physical cache block ?

Answer: C

Correct answer: 64

There are \( 8\ \text{MB}/4\ \text{KB} = 2048 \) main memory blocks and \( 128\ \text{KB}/4\ \text{KB} = 32 \) cache lines. With direct mapping each line is shared by

\[ \frac{2048}{32} = 64 \]

different memory blocks, so any two of those 64 compete for the same line.

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