Computer Network Questions and Answers

Answer: C

Correct answer: Converts \(2^{n}\) input lines into an \(n\)-bit output code

An encoder takes \( 2^{n} \) input lines, of which one is active, and produces the \( n \)-bit binary code identifying which. A decimal-to-BCD encoder, for example, has ten inputs and four outputs. Its inverse is the decoder, described by the second option, which takes an \( n \)-bit code and activates one of \( 2^{n} \) outputs - used for address decoding and for driving displays. A plain encoder assumes only one input is active at a time and produces nonsense if two are. A priority encoder removes that limitation by responding to the highest-numbered active input and ignoring the rest, which is exactly what an interrupt controller needs when several devices request service at once. The third option describes a multiplexer and the fourth a flip-flop. Encoders and decoders together allow a keyboard, with one line per key, to send a compact code over few wires and have it expanded again at the other end.

Answer: B

Correct answer: A + AB = A

The absorption law states A + AB = A, because whenever AB is true A is already true, so the second term adds nothing. It is one of the most useful simplifications when reducing an expression by hand.

Answer: B

Correct answer: True

The statement is true. In a synchronous counter every flip-flop receives the same clock signal at the same instant, and combinational logic on the J and K inputs decides which stages actually change. The contrast is with an asynchronous or ripple counter, in which only the first flip-flop sees the clock and each subsequent stage is clocked by the output of the one before it. The difference is one of speed and of correctness. In a ripple counter the change propagates from stage to stage, so the delays accumulate and the total settling time is the number of stages multiplied by the propagation delay of one. During that interval the counter passes through transient false states, which can produce glitches if the outputs are decoded. A synchronous counter settles in one gate delay regardless of length, and never shows a false intermediate count. The price is more combinational logic, so ripple counters survive where speed does not matter and simplicity does.

Answer: B

Correct answer: True

NAND is functionally complete: a NOT is a NAND with its inputs tied together, an AND is a NAND followed by that inverter, and an OR follows from De Morgan’s theorem. NOR is the other functionally complete gate.

Answer: A

Correct answer: True

The statement is true. The 1’s complement simply changes each 0 to 1 and each 1 to 0, and in hardware it is a row of inverters. The 2’s complement goes one step further: invert every bit and then add 1. That extra step is what makes it the representation actually used for signed integers. The reason for preferring it is practical. 2’s complement has a single representation of zero, whereas 1’s complement has two - 00000000 and 11111111 - which complicates comparison. And 2’s complement addition needs no end-around carry: the same adder handles signed and unsigned values, so subtraction becomes addition of the complement and no separate subtractor is required. In eight bits, 2’s complement covers −128 to +127, the asymmetry arising from that single zero. 1’s complement is still met in checksum calculations, notably in the Internet protocols.

Answer: A

Correct answer: True

The statement is true. An AND gate outputs 1 only when every one of its inputs is 1; if any input is 0 the output is 0. Its Boolean expression is \( Y = A \cdot B \). Its truth table for two inputs runs: 0,0 gives 0; 0,1 gives 0; 1,0 gives 0; 1,1 gives 1. Only the last row gives 1. A useful way to remember it is that AND behaves exactly like ordinary multiplication on the digits 0 and 1, which is why the operation is written with a dot and often called the logical product. OR is correspondingly called the logical sum, though \( 1 + 1 = 1 \) breaks the analogy there. The AND gate is also used as an enable: holding one input at 1 lets the other pass through unchanged, and holding it at 0 blocks the signal. That is how a clock is gated on and off in practice.

Answer: B

Correct answer: True

The statement is true. A NOR gate is an OR gate followed by an inverter, so its output is the complement of OR: since OR gives 0 only when every input is 0, NOR gives 1 only in that case. Its truth table for two inputs runs: 0,0 gives 1; 0,1 gives 0; 1,0 gives 0; 1,1 gives 0. NOR is a universal gate: every logic function can be built from NOR gates alone. Tying both inputs together makes an inverter; a NOR followed by an inverting NOR makes an OR; and by De Morgan’s theorem a NOR fed by two inverters makes an AND. NAND is universal for the same reason. The first integrated circuit computer, the Apollo Guidance Computer, was built almost entirely from three-input NOR gates - a practical demonstration of universality. Two cross-coupled NOR gates also form the simplest SR latch, the basic one-bit memory element.

Answer: B

Correct answer: False

The statement is false - the reverse is true. A ripple counter is slower. In a ripple, or asynchronous, counter only the first flip-flop receives the clock; each later stage is clocked by the output of the one before it. The change therefore propagates along the chain, and the total settling time is the number of stages multiplied by the propagation delay of one. A four-stage counter takes four gate delays to settle. In a synchronous counter every flip-flop is clocked simultaneously and combinational logic decides which stages change, so the whole counter settles in a single delay regardless of length. Speed is not the only difference. While a ripple counter is settling it passes through transient false states, which can produce glitches if the outputs are decoded - a real hazard in control circuits. A synchronous counter never shows a false intermediate count. The ripple counter’s advantage is simplicity: it needs no extra gates at all.

Answer: A

Correct answer: True

A latch responds to its inputs for as long as the enable line is active, whereas a flip-flop samples only at the rising or falling edge of the clock. Edge triggering is what keeps a synchronous circuit’s stages from racing ahead of each other.

Answer: A

Correct answer: True

The statement is true, and it is the standard distinction between the two. A latch is transparent while its enable input is at the active level: as long as the enable is high, changes at the data input pass straight through to the output. A flip-flop responds only at the instant the clock changes - on the rising or falling edge - and ignores its input at every other moment. That difference matters greatly in synchronous design. Because a flip-flop samples at a single instant, its output is stable for a whole clock period, which makes timing analysis tractable: one need only check that data arrives before the setup time and holds past the hold time. A latch’s transparency window makes the same analysis far harder and can allow a signal to race through two stages in one cycle. Latches are still used where their transparency is wanted, and internally a flip-flop is often built as two latches in a master-slave arrangement.