Memory Management Questions and Answers

Answer: D

Correct answer: execute programs larger than the available physical memory

Virtual memory lets a process run without all of it being resident in physical memory. Pages are brought in from disk as they are referenced - demand paging - and pages not currently needed are held on the backing store. A reference to a page that is not resident raises a page fault, a trap the operating system services by finding a free frame, reading the page in, updating the page table and restarting the instruction. Three benefits follow. Programs may be larger than physical memory. More processes fit in memory at once, so CPU utilisation and throughput rise. And less input and output is needed to load a program, since only the parts used are read. The cost is that a page fault takes milliseconds against nanoseconds for a memory access, so the fault rate must stay very low - and if it does not, the system thrashes. It also depends on locality of reference: without it, demand paging would fault constantly.

Answer: A

Correct answer: Digital subscriber line (DSL)

DSL uses the same copper pair as the telephone but transmits at frequencies above the voice band, so it is far faster than a dial-up modem and the line remains usable for calls. Cable and fibre are faster still but do not use the phone line.

Answer: C

Correct answer: a cache of recent page-table entries used to speed up address translation

The TLB is a small, fast associative cache holding recently used page-table entries. It exists to solve a specific problem: without it, every memory reference would need two accesses - one to read the page table and one to fetch the data - halving effective speed. On a TLB hit the frame number is available immediately and only one memory access is needed. On a miss the page table is consulted and the entry is loaded into the TLB, displacing another. Hit rates above 90 per cent are typical because of locality of reference, which brings the effective access time close to that of a single access. It is small - often only tens to a few hundred entries - because associative lookup is expensive in hardware. A context switch is a complication: entries belonging to the old process must not be used by the new one, so the TLB is either flushed or its entries tagged with an address-space identifier. Flushing is why a context switch costs more than it first appears.

Answer: D

Correct answer: All of the above

All three are true of a firewall: it may be implemented in hardware or in software, it examines the traffic crossing a boundary, and what it does with each packet is decided by a configured set of rules.

Answer: B

Correct answer: CPU registers

Registers are the fastest and smallest storage, sitting inside the processor and accessible in a single clock cycle. A processor typically has only a few dozen. The hierarchy descends from there: registers, then cache in several levels, then main memory in DRAM, then secondary storage on solid-state or magnetic disk, then tertiary storage on tape or optical media. At each step capacity rises, cost per bit falls, and speed falls - often by an order of magnitude or more. The hierarchy works only because of locality of reference. Programs concentrate their accesses in small regions of address space, so keeping the active region near the top gives most references the speed of the fast level at the cost of the slow one. Without locality the whole arrangement would be pointless. Volatility changes at the boundary between main memory and secondary storage: everything above loses its contents when power is removed. Registers are managed by the compiler, cache by hardware, and main memory by the operating system.

Answer: C

Correct answer: It holds copies of data from main memory that are likely to be used again

Cache holds copies of recently or frequently used data and instructions from main memory, so that repeat accesses are served in a few cycles rather than hundreds. It works because of the principle of locality. Temporal locality means a location just used is likely to be used again shortly; spatial locality means neighbouring locations are likely to be needed next, which is why data is fetched in whole cache lines rather than single bytes. It is faster and smaller than main memory, not slower and larger, so the third option is exactly backwards - it is built from SRAM, which uses several transistors per bit and needs no refreshing, against the single capacitor of DRAM. It is managed entirely by hardware and is transparent to the programmer, unlike main memory, which the operating system allocates, and registers, which the compiler assigns. That transparency is why cache behaviour must be inferred from performance rather than controlled directly. Modern processors use three levels, L1 through L3.

Answer: A

Correct answer: Token

In a token ring only the station holding the token may transmit, and it passes the token on when finished. That is how the topology avoids collisions without any contention.

Answer: C

Correct answer: avoid allocating a large contiguous table for the whole address space

A hierarchical or multilevel page table exists to avoid keeping one enormous contiguous table per process. The arithmetic makes the problem plain. A 32-bit address space with 4 KB pages contains a million pages, and at four bytes per entry the table is 4 MB - per process, and required to be contiguous in physical memory. That is unacceptable. Splitting it into two levels means only the outer table and the inner tables covering parts of the address space actually in use need exist; the rest are simply absent. Since most processes use a small and scattered fraction of their address space, the saving is very large. The cost is an extra memory access per translation, so it makes translation slower rather than faster - which is why the second option is wrong and why the TLB is essential rather than dispensable. 64-bit architectures need three or four levels. The alternatives are hashed page tables and inverted page tables, which trade the search cost differently.

Answer: B

Correct answer: a process spends more time paging than executing

Thrashing is the state in which a process spends more time servicing page faults than doing useful work. It arises when a process has too few frames to hold its working set - the pages it is actively using - so each reference evicts a page that will be needed almost immediately. What makes it pathological is the feedback loop. The operating system sees low CPU utilisation and concludes that more processes should be admitted; that reduces the frames available to each; more page faults follow; utilisation falls further. Throughput collapses rather than degrading gracefully. The remedies attack the cause rather than the symptom. The working set model allocates each process enough frames for the pages it has referenced in a recent window, suspending processes that cannot be given enough. Page-fault frequency control adjusts allocation directly, adding frames when the fault rate rises and removing them when it falls. Simply adding physical memory also helps, which is why thrashing is far less common than it was.

Answer: D

Correct answer: The set of pages held with n frames is always a subset of the set held with n+1 frames

A stack algorithm is one for which the set of pages in memory with \( n \) frames is always a subset of the set that would be in memory with \( n+1 \) frames, for the same reference string. That property has an immediate consequence: a stack algorithm can never suffer Belady’s anomaly. Since more frames can only add pages and never remove ones that would have been kept, the fault count cannot rise as frames are added. LRU and the optimal algorithm are both stack algorithms - LRU because it keeps the \( n \) most recently used pages, and the \( n \) most recent are always among the \( n+1 \) most recent. FIFO is not, which is exactly why it can exhibit the anomaly: age of loading bears no such nesting relation. The name refers to the mathematical property rather than to any data structure, and no stack is involved in the implementation.