Computer Network Questions and Answers

Answer: D

Correct answer: 3

A full adder has three inputs - the two bits to be added and a carry-in from the previous stage - and two outputs, the sum and the carry-out. The carry-in is what distinguishes it from a half adder, which has only two inputs and cannot be used beyond the least significant bit of a multi-bit addition. Its Boolean expressions are \[ S = A \oplus B \oplus C_{in}, \qquad C_{out} = AB + C_{in}(A \oplus B), \] and it can be built from two half adders and an OR gate. The sum output is 1 when an odd number of the three inputs is 1, which is why it is a cascade of XOR gates; the carry is 1 when at least two of the three are. Chaining \( n \) full adders gives a ripple-carry adder for \( n \)-bit numbers, simple but slow because each stage waits for the carry below it. Carry-lookahead adders compute the carries in parallel to remove that delay.

Answer: A

Correct answer: 1011

Take the 1’s complement by inverting every bit, giving 1010, then add 1 to get 1011. This representation lets a computer perform subtraction using the same adder circuit it uses for addition.

Answer: C

Correct answer: detect single-bit errors

A parity bit is an extra bit appended to a group of data bits so that the total number of 1s is even, in even parity, or odd, in odd parity. The receiver recomputes it and compares. It detects a single-bit error but cannot correct it, because it shows that something is wrong without indicating which bit. And it fails entirely on an even number of errors, since two flipped bits leave the parity unchanged - which is its principal limitation. It is generated in hardware by a cascade of XOR gates, whose output is 1 exactly when the number of 1s is odd. Stronger schemes exist for more demanding work. Hamming codes use several parity bits over overlapping groups and can locate and correct a single-bit error. Cyclic redundancy checks detect burst errors far more reliably and are what network frames and storage media actually use. Parity survives in memory modules and serial links, where it is cheap and usually sufficient.

Answer: D

Correct answer: 10

With \( n \) address lines a processor can select \( 2^{n} \) distinct locations. Since 1 KB in the binary sense is 1,024 bytes, \[ 2^{n} = 1024 \quad\Rightarrow\quad n = 10. \] The powers of two are worth having by heart for this family of questions: \( 2^{10} = 1\text{K} \), \( 2^{20} = 1\text{M} \), \( 2^{30} = 1\text{G} \). So 1 MB needs 20 address lines and 4 GB needs 32 - which is precisely why a 32-bit processor can address no more than 4 GB without extensions. The distractor 1024 confuses the number of locations with the number of lines needed to select among them. The width of the data bus is a separate matter: it determines how many bits are transferred at once, not how many locations exist. A memory of 1K × 8 has ten address lines and eight data lines.

Answer: D

Correct answer: 4

A binary counter with \( n \) flip-flops passes through \( 2^{n} \) distinct states, so a modulus-16 counter needs \[ 2^{n} = 16 \quad\Rightarrow\quad n = 4. \] Each flip-flop stores one bit, and four bits represent the sixteen values 0000 to 1111 - decimal 0 to 15. The general rule is worth remembering in both directions: for a required modulus \( N \), the number of flip-flops is the smallest \( n \) with \( 2^{n} \ge N \). A decade counter of modulus 10 therefore still needs four flip-flops, and the six unused states are removed by feedback that resets the counter at a count of ten. Counters divide as well as count: a modulus-16 counter’s most significant output is the clock frequency divided by 16, which is why they are used as frequency dividers. An asynchronous or ripple counter clocks each stage from the previous one and is simpler but slower; a synchronous counter clocks every stage together and avoids the accumulated delay.

Answer: A

Correct answer: NAND

By De Morgan's law \( \overline{A}+\overline{B} = \overline{A\cdot B} \), which is the NAND function. It is the expression for a NAND written with the inversion pushed inwards onto the variables.

Answer: D

Correct answer: 13

Each position carries a power of two: \(1101_2 = 8 + 4 + 0 + 1 = 13\). The zero in the twos place is what separates it from 1111, which would be 15.

Answer: C

Correct answer: 8

A decoder with \(n\) input lines activates one of \(2^n\) outputs, so a 3-to-8 decoder has eight outputs. Exactly one output is asserted at a time, corresponding to the binary value on the three inputs.

Answer: B

Correct answer: XOR gate

A half adder adds two bits and produces SUM = A ⊕ B from an XOR gate, while CARRY = A · B comes from an AND gate. XOR is the right choice because the sum bit is 1 exactly when the two inputs differ.

Answer: D

Correct answer: 8

A decoder activates exactly one output for each combination of its inputs, so \( n \) input lines give \( 2^{n} \) outputs. With three inputs that is \[ 2^{3} = 8. \] Such a device is called a 3-to-8 decoder. Its principal use is address decoding: the address lines of a processor are fed to a decoder whose outputs act as chip-select signals, so that exactly one memory or peripheral device responds to any given address. Decoders usually have an enable input, which allows several to be cascaded to decode a larger address space. The inverse device is an encoder, which takes \( 2^{n} \) inputs and produces an \( n \)-bit code. A priority encoder resolves the case of several inputs being active at once by responding to the highest, which is how interrupt controllers work. A related device is the seven-segment decoder, which converts a four-bit BCD digit into the seven signals that drive a display.