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GATE EC Syllabus, Exam Pattern, Eligibility, Important Dates

186 topics across 11 subjects. Every question carries a written explanation.

GATE EC is the Electronics and Communication Engineering paper of GATE. The test is set each year by one of IISc and the seven older IITs for the National Coordination Board, Ministry of Education. IIT Madras has the job for 2027.

After CS, EC is the largest engineering paper: 1,15,448 registered in 2026 and 95,752 turned up. Even so, it was held as one session that year, so no normalisation applied.

A GATE EC score, valid for three years, is used for M.Tech and PhD admission in electronics, communication, VLSI and signal processing, and by PSUs such as BSNL, ECIL and POWERGRID when they recruit. Registration for 2027 has closed; the exam is in February 2027 and results are on 19 March 2027.

Last checked against the official notification on .

GATE EC Details

Exam Pattern
ModeComputer based test
Duration3 hours
LanguageEnglish
Questions65 (10 General Aptitude, 55 subject)
MarksGeneral Aptitude 15, Engineering Mathematics 13, Electronics and Communication subject 72; total 100
Question typesMCQ, MSQ, NAT; each worth 1 or 2 marks
Wrong MCQ−1/3 (1-mark), −2/3 (2-mark)
Wrong MSQ or NATno deduction

You can't lose marks on MSQs or NATs. MCQs carry negative marking, and MSQs give credit only when your choice matches the full set of right options. Use the on-screen calculator for NATs; no other calculator is allowed in the hall.

Two-paper option

EC as the primary paper can be paired with CS, DA, EE, IN, PH or RA.

Syllabus

Based on IIT Madras's EC syllabus for GATE 2027.

Engineering Mathematics

Vector spaces, rank and eigenvalues; mean value theorems, multiple and line integrals, Taylor series; linear ODEs, variation of parameters, separable PDEs; gradient, divergence, curl and the Gauss, Green and Stokes theorems; analytic functions, Cauchy's formula, Laurent series and residues; probability distributions, correlation and regression.

Networks, Signals and Systems

Node and mesh analysis and network theorems; phasors and maximum power transfer; RLC transients via Laplace; two-port parameters; LTI systems, convolution, poles and zeros, group and phase delay; Fourier series and transform, sampling; DTFT, DFT, z-transform, FIR and IIR filter design.

Electronic Devices

Energy bands, carrier concentration, drift and diffusion, generation and recombination, Poisson and continuity equations; P-N junction, Zener, BJT, MOS capacitor, MOSFET and scaling, LED, photodiode, solar cell.

Analog Circuits

Clippers, clampers and rectifiers; BJT and MOSFET biasing, small-signal analysis and frequency response; current mirrors and differential amplifiers; op-amp circuits, active filters, oscillators, Miller compensation and phase margin.

Digital Circuits

Number formats, Boolean minimisation and K-maps, static CMOS gates, arithmetic circuits, muxes and decoders; latches, flip-flops, counters, FSMs, setup and hold time and critical path; ADCs and DACs; ROM, SRAM, DRAM; instruction sets, datapath and pipelining.

Control Systems

Transfer functions, block diagrams, signal flow graphs, transient and steady state response, Routh-Hurwitz, Nyquist, Bode and root locus, compensators and PID, state equations.

Communications

Random processes and PSD; AM and FM; entropy, source coding and channel capacity; PCM, DPCM, ASK, PSK, FSK, QAM, ISI, MAP and ML detection, matched filters, SNR and BER; Hamming codes and CRC.

Electromagnetics

Maxwell's equations, Poynting vector, plane wave reflection, polarisation and skin depth; transmission lines, S-parameters and the Smith chart; waveguides, optical fibres, dipole and monopole antennas, arrays.

General Aptitude

Common to all papers, 15 marks: verbal, quantitative, analytical and spatial ability.

Eligibility Criteria

You need to be in at least the third year of a bachelor's programme, or have completed a government-approved degree in engineering, technology, architecture, science, commerce, arts or humanities. M.Sc and MCA students can sit from the first year, and IETE or AMIE candidates once they have cleared Section A. There's no upper age limit.

The degree needn't be in electronics for GATE; it matters only to the institute or employer using your score.

How to Apply
CategoryOne paper, regularTwo papers, regularOne paper, late feeTwo papers, late fee
Female, SC, ST, PwD₹1,000₹2,000₹1,500₹2,500
Everyone else, including foreign nationals₹2,000₹4,000₹2,500₹4,500

Everything happens on GOAPS. Indian applicants were advised to sign in with a verified DigiLocker account, and the site took a live photo at registration. Up to 21 October 2026 you can edit your category, paper or city choices on GOAPS; the usual charge is ₹500 per paper.

Participating Institutes

M.Tech admissions at IITs and IISc go through COAP, and at NITs through CCMT. Admitted GATE students at government institutes get a ₹12,400 monthly assistantship.

For jobs, the GATE site's PSU list includes BSNL, ECIL, BHEL, HAL, POWERGRID, NTPC and NPCIL. Each employer's notification says which papers it accepts in a given year.

Exam Centres

Centres are spread across 300-plus Indian cities, grouped into eight zones. Your three city choices had to fall in one zone, and IIT Madras may place you elsewhere if capacity runs short. The allotted city is notified on 4 January 2027.

Important Dates

GATE 2027 schedule from IIT Madras; dates may change.

StageDate
Application portal (GOAPS) opened2 September 2026
Regular registration closed5 October 2026
Late fee registration closed12 October 2026
Special late fee window15 October 2026, 10:30 AM to 16 October 2026, 10:29 AM
Application rectification14 to 21 October 2026
Exam city announced4 January 2027
Admit cardnot yet announced
Exam days6, 7, 13, 14, 20 and 21 February 2027
Result19 March 2027

Forenoon sessions run 9:30 to 12:30 and afternoon ones 2:30 to 5:30. Which slot EC gets is still to be notified.

Admit Card

Download it from GOAPS when IIT Madras releases it; the date isn't fixed. It names your centre, date and session. Bring the original photo ID you listed. Entry starts 40 minutes ahead, and login is blocked 15 minutes after the start time.

Result

IIT Madras publishes responses and a provisional key first, then the final result on 19 March 2027. The GATE Score is out of 1000 and lasts three years. Download the scorecard during the free period; afterwards it costs ₹500, and none are issued after 31 December 2027.

Cut Off
GATE 2026, ECFigure
Registered1,15,448
Appeared95,752
Qualifying mark, General26.4
Qualifying mark, OBC-NCL / EWS23.7
Qualifying mark, SC / ST / PwD17.5

The General qualifying mark equals the paper's mean plus one standard deviation, kept within 25 to 40. OBC-NCL/EWS get 90% of it and SC/ST/PwD two-thirds. Qualifying just gets you a score; IITs, NITs and PSUs then pick their own cut-offs, usually well above these.

Preparation Tips
  1. Networks and signals feed into control and communications. Learn them first.
  2. Analog and digital circuits together carry a lot of marks; solve plenty of small-signal and timing problems.
  3. Electromagnetics puts many people off. Transmission lines and the Smith chart are the most predictable part of it.
  4. The digital section also covers computer organisation and pipelining, so go through them.
  5. Guess on MSQs and NATs if you have to; they carry no penalty.
  6. Work through the EC 2024 to 2026 papers on the official download page in three-hour sittings.
Official Links
Frequently Asked Questions

Who conducts GATE EC 2027?

IIT Madras, for the National Coordination Board.

How many people take GATE EC?

95,752 appeared in 2026, out of 1,15,448 registered.

What did you need to qualify in 2026?

26.4 marks (General), 23.7 (OBC-NCL/EWS), 17.5 (SC/ST/PwD).

Which second paper goes with EC?

CS, DA, EE, IN, PH or RA.

Is it too late to register?

Yes. The last window closed on 16 October 2026.

Does a good EC score guarantee a PSU job?

No. PSUs shortlist on GATE scores and then hold their own interviews or tests.