Phase Locked Loop Questions and Answers

Answer: A

The phase error must stay between 0 and π.

In a phase locked loop, the phase detector converts the phase difference between the VCO output and the incoming signal into a control voltage. For the common XOR-type detector, the average output rises linearly as the phase error goes from 0 to \(\pi\) and then falls again from \(\pi\) to \(2\pi\). The loop can correct the VCO only while the error stays on the rising part, 0 to \(\pi\), with the locked operating point normally near \(\pi/2\).

Outside that range the slope reverses, so the feedback has the wrong sign and lock is lost. The ranges 0 to \(\pi/2\), 0 to \(2\pi\) and \(\pi\) to \(2\pi\) are not the monotonic range of that characteristic.

Answer: D

The statement that is not true is the VCO input is always zero when locked.

In a phase locked loop, the phase detector compares the input with the VCO output, and the filtered error voltage drives the VCO. When locked, the VCO frequency equals the input frequency and tracks it, and the phases are held in a fixed relationship, so statements A, B and C describe a locked loop.

The VCO control voltage is zero only if the input happens to be at the VCO's free-running frequency. For any other input frequency within the lock range, a non-zero control voltage, produced by a small steady phase error, is exactly what holds the VCO at the input frequency.

Answer: B

For a phase locked loop, the lock range is greater than the capture range.

The capture range is the band of input frequencies over which an unlocked PLL can acquire lock. The lock (tracking) range is the band over which a PLL that is already locked can follow a changing input frequency. Once locked, the loop can track further than it could capture from the unlocked state, so the lock range is the wider of the two.

During lock the VCO frequency equals the input frequency, not exceeds it, and the VCO control voltage is generally non-zero, since it is what holds the VCO at the input frequency.

Answer: C

The correct code is (2) (3) (4) (1).

• (a) The error signal comes from the phase detector, which compares the input and VCO phases.
• (b) The control signal comes from the loop filter, which smooths the error signal.
• (c) The output signal is produced by the voltage controlled oscillator.
• (d) The input signal is the modulated signal the PLL locks on to.

Options B and D start the loop at the VCO, and option A swaps the loop filter and the VCO.

Answer: B

The lock range is 100 kHz.

The lock range is the band of input frequencies over which a PLL, once locked, can follow the input. That is limited by the range the VCO can actually cover, here 350 kHz to 450 kHz:

\[ 450 - 350 = 100\ \text{kHz} \]

350 kHz and 450 kHz are the edges of the range, not its width, and 200 kHz is twice the span the VCO can actually cover, so the loop could not stay locked over it.

Answer: B

Phase noise is the undesirable random fluctuations in the phase of the output signal.

An ideal PLL or oscillator output would be a pure line in the spectrum. In practice noise in the VCO, the reference, the phase detector and the loop filter makes the zero crossings jitter randomly, which spreads energy into sidebands around the carrier. Phase noise is specified as the power in a 1 Hz band at a given offset, relative to the carrier, in dBc/Hz. It is the frequency-domain view of timing jitter.

The steady phase difference between reference and feedback, or between the comparator's inputs, is the phase error that the loop uses to stay locked, not noise. Intentional modulation of the VCO is a deliberate signal, so it is the opposite of noise.

Answer: A

A PLL maintains lock by comparing the phase of two signals.

A phase-locked loop has a phase detector, a loop filter and a voltage-controlled oscillator. The phase detector compares the phase of the input (reference) signal with the phase of the VCO output, or a divided-down copy of it, and produces an error voltage proportional to the difference. Filtered, this voltage steers the VCO so that the phase difference stays constant. A constant phase difference means the frequencies are exactly equal, which is what lock is.

Equal frequency is therefore the result of phase comparison, not the quantity compared. Comparing amplitudes, between two signals or against a threshold, is what a comparator or AGC circuit does.

Answer: A

Fractional-N synthesis uses fractional values in the frequency divider to achieve finer frequency resolution.

In an integer-N PLL the output is N times the reference frequency, so the channel spacing equals the reference frequency. A fractional-N synthesiser switches the divider between N and N+1 (usually under control of a sigma-delta modulator) so that the average division ratio is a fraction. Output steps much finer than the reference become possible while the reference, and so the loop bandwidth, stays high.

Better phase noise and faster lock can follow from that higher reference, but the defining purpose is resolution; the divider switching itself creates fractional spurs that must be suppressed, so it is not a technique to eliminate spurs. Fractional values of the VCO control voltage are meaningless, since that voltage is continuous anyway.

Answer: C

A phase lock loop is used for the detection of FM, the third option. The loop locks its voltage-controlled oscillator to the incoming signal, and the control voltage that holds the lock follows the instantaneous frequency of the signal, so it is the demodulated message.

Plain AM carries its information in amplitude, which a phase detector does not follow, so a PLL is not the usual detector for AM or QAM. PM is related, but the standard use of the loop in the key is for FM detection.