Analog to Digital Converters Questions and Answers

Answer: A

Both statements are true and the reason explains the assertion (option A). A flash (parallel comparator) ADC of N bits uses \(2^N - 1\) comparators, one for each threshold between the \(2^N\) levels, and all the comparators work at the same time.

Because everything is done in one step, the conversion time is just the delay of one comparator plus the encoder, so the speed of the comparator limits the speed of the converter. The reason therefore tells why the structure is fast, and it follows from the assertion.

Answer: B

The key is uses same capacitor for charge and discharge.

In the first phase the integrator charges through \(R\) for a fixed time \(T_1\). In the second phase the same \(R\) and the same \(C\) discharge it to zero in time \(T_2\). The two slopes are \(v'_A/RC\) and \(V_{\mathrm{REF}}/RC\), so the factor \(RC\) cancels in \(T_2 = T_1\,v'_A/V_{\mathrm{REF}}\). Any error or drift in \(R\) or \(C\) therefore has no effect on the result, and the conversion stays linear and accurate.

That the ramps are straight lines (A) is a property of an integrator, not the reason the whole conversion is linear. A good comparator (C) and a good op-amp (D) help accuracy but do not explain it.

Answer: C

The key is starting of A/D operation.

S1 is the reset switch across the integrator capacitor. While it is closed, \(C\) is held discharged. The passage says that at \(t = 0\) the reset switch S1 opens and the negative input is applied to the integrator, so opening S1 is what lets the ramp begin and the conversion start.

Option A is wrong: nothing is discharged at the end of \(T_1\), since the ramp turns downward there when S2 switches to \(V_{\mathrm{REF}}\). Option D is wrong because overflow of the counter is what ends \(T_1\), not a reset of S1. Option B is the closest rival, since closing S1 after the conversion does clear any leftover charge. But the integrator output is already at zero when the count stops, and the passage describes S1 only at the start, which is why the key picks C.

Answer: C

The converted output depends upon \(T_2\).

The counter runs during \(T_2\) and its count is the digital output. From the passage, \(T_2 = T_1\,(v'_A/V_{\mathrm{REF}})\). \(T_1\) is fixed and \(V_{\mathrm{REF}}\) is a constant, so \(T_2\), and with it the count, is proportional to the analog input \(v'_A\).

\(R\) and \(C\) set both slopes and cancel out of that relation, so the output does not depend on them (A and B are wrong). \(T_1\) is a fixed interval, the time for the counter to fill, so it does not carry the information (D is wrong).

Answer: B

The answer in the key is Dual slope A/D.

The dual-slope converter integrates the input for a fixed time and then measures how long a reference takes to bring the integrator back to zero. Because both slopes use the same resistor, capacitor and clock, their values cancel out, so the circuit is simple and very accurate, reaching resolutions of 16 to 20 bits. It is the principle used in digital voltmeters and multimeters.

A flash converter is the fastest but needs \(2^{n} - 1\) comparators, so it is neither simple nor high in resolution. A successive approximation converter is fast but usually limited to about 8 to 16 bits, and a counting converter is simple but slow.

Answer: B

The half-LSB offset is added to reduce the maximum quantization error.

Without the offset, a successive approximation converter truncates: every input between two code levels is rounded down, so the error ranges from 0 to almost 1 LSB. Shifting the D/A comparison levels by half an LSB makes the converter round to the nearest level instead, so the error lies between -1/2 and +1/2 LSB and its maximum magnitude halves.

The offset does not change the number of comparisons, so it does not affect speed; it does not add output bits; and it does not widen the input range, since the full-scale code is unchanged.

Answer: A

A 3½ digit multimeter generally uses a 12 bit dual slope ADC.

A 3½ digit display reads up to ±1999, about 2000 counts, which needs a resolution of at least 11 bits (\(2^{11} = 2048\)); a 12-bit-class converter covers it. Digital multimeters use the dual slope (integrating) method because it is accurate, cheap and rejects mains-frequency noise by integrating over a whole number of cycles; speed does not matter for a meter that updates a few times a second. Single-chip converters such as the ICL7106 are built for exactly this.

An 8-bit converter gives only 256 levels, far too few for 2000 counts, whatever its type, so all three 8-bit options are wrong.

Answer: C

The slowest converter is the Integrating type.

An integrating (dual-slope) converter integrates the input for a fixed time and then measures how long a reference voltage takes to bring the integrator back to zero. Each conversion takes up to twice the full count of its counter, typically tens of milliseconds, which is why it is used in digital voltmeters where accuracy and noise rejection matter more than speed.

The counting (ramp) type needs up to one full count per conversion, the successive approximation type only one clock period per bit, and the parallel comparator (flash) type converts in a single step, making it the fastest.

Answer: C

The substitute is a voltage to frequency convertor.

A voltage to frequency converter turns an analog voltage into a pulse train whose frequency is proportional to the voltage. Counting those pulses over a fixed time gives a digital number proportional to the input, so a V/F converter with a counter performs analog to digital conversion. It is used in this way in digital voltmeters and in isolated or remote measurement.

A frequency to voltage converter works the other way. An astable multivibrator only generates a fixed square wave, and a voltage regulator holds a voltage steady; neither converts an analog value into a digital one.

Answer: B

In order of increasing speed: dual slope, successive approximation, flash.

A dual slope ADC integrates the input for a fixed time and then de-integrates against a reference, taking milliseconds per conversion; it is slow but accurate and rejects noise, which is why it is used in digital multimeters. A successive approximation ADC finds one bit per clock cycle, so an n-bit conversion takes about n clock cycles, typically microseconds. A flash ADC compares the input with all levels at once using 2ⁿ − 1 comparators, converting in a single step of nanoseconds.

Every other order puts one of these out of place, for example listing flash as the slowest.