Discussion
The size of the physical address space of a processor is 232 bytes. The capacity of a cache memory unit is 223 bytes. The cache block size is 128 bytes. The cache memory unit can be built as a direct mapped cache or as a K-way set-associative cache, where K = 2L and L ∈ {1, 2, 3}. Let the length of the TAG field be M bits for the direct mapped cache, and N bits for the set-associative cache.
Which one of the following options is true?
Answer: A
The relation is N = M + L.
The block offset needs 7 bits (128 = \(2^{7}\)), and the cache holds \(2^{23}/2^{7} = 2^{16}\) blocks.
\[ \begin{aligned} \text{Direct mapped: } M &= 32 - 16 - 7 = 9 \\ \text{sets} &= 2^{16}/2^{L} = 2^{16-L} \\ \text{Set-assoc.: } N &= 32 - (16-L) - 7 = 9 + L \end{aligned} \]
Each doubling of associativity halves the number of sets, removing one index bit and adding it to the tag, so the tag grows by L bits, not by K = \(2^{L}\). The tag never shrinks with higher associativity, which rules out both subtraction options.
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