Discussion
The size of the physical address space of a processor is \(2^{P}\) bytes. The word length is \(2^{W}\) bytes. The capacity of cache memory is \(2^{N}\) bytes. The size of each cache block is \(2^{M}\) words. For a \(K\)-way set-associative cache memory, the length (in number of bits) of the tag field is
Answer: B
The tag field has \(P - N + \log_{2} K\) bits.
The physical address has \(P\) bits. A block is \(2^{M}\) words of \(2^{W}\) bytes, so the block offset is \(M + W\) bits. The cache holds \(2^{N} / 2^{M+W}\) blocks, grouped \(K\) to a set:
\[ \begin{aligned} \text{sets} &= 2^{N - M - W} / K \\ \text{index} &= N - M - W - \log_{2} K \\ \text{tag} &= P - \text{index} - (M + W) \\ &= P - N + \log_{2} K \end{aligned} \]
Check: a direct-mapped cache (\(K = 1\)) gives a tag of \(P - N\) bits, and higher associativity means fewer sets and so a longer tag. \(P - N - \log_{2} K\) gets that direction wrong, and the options with \(- M - W\) subtract the block offset twice.
Post your comment
Please log in or register to post a comment.
Examination Categories
- SSC Exams
- Banking Exams
- Teaching Exams
- Civil Services Exams
- Railways Exams
- Engineering Recruitment Exams
- Defence Exams
- State Government Exams
- Police Exams
- Insurance Exams
- Nursing Exams
- Other Government Exams
- NRA CET
- PG Entrance Exams
- Campus Placement
- MBA Entrance Exams
- CUET and UG Entrance
- Judiciary Exams
- Regulatory Body Exams
- Software Development