Discussion
The circuit diagram shown in figure represents :
Answer: C
The circuit is a two input CMOS NOR gate.
The output X is pulled up to VDD only through two p-MOS transistors in series, so it goes high only when both are on, that is, when A and B are both 0. The two n-MOS transistors in parallel pull X down to VSS whenever either A or B is 1. The output is therefore 1 only for A = B = 0:
\[ X = \overline{A + B} \]
A NAND gate has the opposite arrangement, p-MOS in parallel and n-MOS in series. AND and OR gates need an extra inverter stage after the NAND or NOR, which this single-stage circuit does not have.
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