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Assertion (A) : A half-adder is faster than full-adder.
Reason (R) : A half-adder gives only one output while a full adder gives two outputs.

  • A.Both (A) and (R) are true and (R) is the correct explanation of (A).
  • B.Both (A) and (R) are true, but (R) is not the correct explanation of (A).
  • C.(A) is true and (R) is false.
  • D.(A) is false and (R) is true.

Answer: C

A half adder is simpler and has fewer gates in the path, so it is faster than a full adder, and (A) is true. (R) is false, since a half adder gives two outputs, sum and carry, as does a full adder. So (R) is false and cannot explain (A). A full adder must add the carry coming from the previous stage as well, so its signal passes through two half-adder stages and an OR gate, and it is slower, not faster. That the half adder is faster is true, but the stated reason for it is wrong, so the reason cannot be the explanation. The answer is (A) is true and (R) is false.

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