Discussion
In a D flip-flop, the output Q after a clock edge is equal to
Answer: B
Correct answer: the value of D just before the clock edge
A D flip-flop simply captures whatever is on its D input at the active clock edge and holds it until the next one. Its characteristic equation is \( Q_{next} = D \). The D stands for data or delay, and both readings are apt: the device stores one bit of data, and it delays a signal by exactly one clock period. Its virtue is that it has no forbidden or ambiguous input combination, unlike the SR flip-flop, and needs no input decoding, unlike the JK. That simplicity is why it is the workhorse of synchronous design and why registers, shift registers and pipeline stages are built from it. For the capture to be reliable the D input must be stable for the setup time before the edge and the hold time after it. Violating either can leave the output metastable - hovering between levels for an unpredictable period - which is why an asynchronous input is passed through two D flip-flops in series before being used.
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