Discussion
In a half adder, the SUM output is generated by which gate?
Answer: D
Correct answer: XOR
A half adder adds two single bits and produces two outputs. The SUM is generated by an XOR gate and the CARRY by an AND gate: \[ S = A \oplus B, \qquad C = A \cdot B. \] The reason is visible in the arithmetic. 0+0 gives sum 0; 0+1 and 1+0 give sum 1; and 1+1 gives sum 0 with a carry of 1. The sum column is 1 exactly when the inputs differ, which is the definition of XOR, and the carry column is 1 only when both are 1, which is AND. The half adder cannot accept a carry from a previous stage, which is why a full adder is needed for multi-bit addition. A full adder takes three inputs and can be built from two half adders and an OR gate. Chaining full adders gives a ripple-carry adder, simple but slow because each stage waits for the carry from the one below; carry-lookahead adders exist to remove that delay.
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