Discussion
In a positive-edge-triggered flip-flop, the output changes on the falling edge of the clock.
Answer: B
Correct answer: False
The statement is false. A positive-edge-triggered flip-flop responds on the rising edge of the clock - the transition from low to high. A negative-edge-triggered device responds on the falling edge. On a circuit diagram the two are distinguished by a small triangle at the clock input, with an added inversion bubble marking negative-edge triggering. The choice between them is a design convention rather than a matter of correctness, but mixing the two in one design creates a half-cycle timing difference that must be accounted for, and is a common source of error. Two timing requirements attach to either kind. The data must be stable for the setup time before the active edge and for the hold time after it. Violating them can leave the flip-flop metastable, hovering between levels for an unpredictable interval - the reason asynchronous inputs are passed through two flip-flops in series before use.
Post your comment
Please log in or register to post a comment.
Examination Categories
- SSC Exams
- Banking Exams
- Teaching Exams
- Civil Services Exams
- Railways Exams
- Engineering Recruitment Exams
- Defence Exams
- State Government Exams
- Police Exams
- Insurance Exams
- Nursing Exams
- Other Government Exams
- NRA CET
- PG Entrance Exams
- Campus Placement
- MBA Entrance Exams
- CUET and UG Entrance
- Judiciary Exams
- Regulatory Body Exams
- Software Development