Discussion
In an SR flip-flop, setting both S and R to 1 produces a valid, predictable output.
Answer: A
Correct answer: False
The statement is false. With both S and R at 1 the SR flip-flop enters its forbidden or invalid condition. The problem is twofold. While both inputs are held high, Q and its complement are driven to the same level, so the outputs are no longer complementary and the device is not storing a meaningful bit. Worse, when the inputs are released together the circuit settles into whichever state wins a race between its two gates, which depends on minute differences in propagation delay - so the resulting state is genuinely unpredictable. The JK flip-flop was designed to remove this defect. By feeding the outputs back into the input gating, it converts the J = K = 1 case into a useful toggle, and that toggle is what makes binary counters possible. The D flip-flop avoids the problem differently, by deriving both internal inputs from a single data line so the forbidden combination can never arise.
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