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Consider a sequential digital circuit consisting of T flip-flops and D flip-flops as shown in the figure. CLKIN is the clock input to the circuit. At the beginning, Q1, Q2 and Q3 have values 0, 1 and 1, respectively.

A T flip-flop, a D flip-flop and a T flip-flop in a row on a common clock CLKIN; Q1 drives D, Q2 drives the second T, and Q3 through an inverter drives the first T

Which one of the given values of (Q1, Q2, Q3) can NEVER be obtained with this digital circuit?

  • A.(0, 0, 1)
  • B.(1, 0, 0)
  • C.(1, 0, 1)
  • D.(1, 1, 1)

Answer: A

The state that can never occur is (0, 0, 1).

All three flip-flops share CLKIN. From the figure, the first T input is \(\overline{Q3}\), the D input is Q1, and the second T input is Q2. So at each clock edge:

\[ \begin{aligned} Q1^{+} &= Q1 \oplus \overline{Q3} \\ Q2^{+} &= Q1 \\ Q3^{+} &= Q3 \oplus Q2 \end{aligned} \]

Starting from (0, 1, 1), the states run 011, 000, 100, 010, 101, 111, 110, and then back to 011. That cycle holds seven of the eight states; the missing one is 001.

(1, 0, 0) appears after the second clock, (1, 0, 1) after the fourth and (1, 1, 1) after the fifth, so they can all be obtained.

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