Discussion
The gate delay is proportional to :
Answer: A
The gate delay is proportional to Ron.Cg.
A logic gate's delay is the time its driving transistor takes to charge or discharge the capacitance on its output node. The transistor in its on state acts as a resistance \(R_{on}\), and the load is mainly the gate capacitance \(C_{g}\) of the next stage's inputs. The output therefore changes like an RC circuit, with time constant
\[ \tau = R_{on} C_{g} \]
This is the basis of the standard estimate of inverter delay in Pucknell and Eshraghian's VLSI text, where a stage delay is expressed in units of \(\tau\).
Source resistance, drain resistance and drain-substrate or gate-source capacitances alone are not the controlling terms, and \(C_{ox}\) is capacitance per unit area, not the load capacitance of the node.
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