Discussion
An engineer reports an interrupt latency of 2 ns on a 16 MHz microcontroller. The proper response is that
Answer: C
Correct answer: the figure is impossible, one cycle alone being 62.5 ns
At 16 MHz a single clock cycle is \[ \frac{1}{16\times10^{6}} = 62.5\ \mathrm{ns}, \] and taking an interrupt costs at least a handful of cycles for recognition, vector fetch and context save. A latency of 2 ns is a small fraction of one cycle and therefore impossible on this part - the figure has probably been quoted in cycles and mislabelled as nanoseconds.
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