Discussion
Race Around condition can be avoided in digital logic circuits using :
Answer: D
The race-around condition is avoided by a master slave JK flip-flop.
In a level-triggered JK flip-flop with J = K = 1, the output toggles and the new output is fed straight back to the gates while the clock is still high, so it toggles again and again for as long as the clock pulse lasts. The final state is unpredictable. In the master-slave arrangement the master accepts the inputs while the clock is high, and the slave copies the master only when the clock goes low. The fed-back output therefore cannot change during the time the master is enabled, and the flip-flop toggles exactly once per clock pulse.
Edge triggering is the other cure. A shift register, full adder or AND gate does nothing to stop the repeated toggling.
Post your comment
Please log in or register to post a comment.
Examination Categories
- SSC Exams
- Banking Exams
- Teaching Exams
- Civil Services Exams
- Railways Exams
- Engineering Recruitment Exams
- Defence Exams
- State Government Exams
- Police Exams
- Insurance Exams
- Nursing Exams
- Other Government Exams
- NRA CET
- PG Entrance Exams
- Campus Placement
- MBA Entrance Exams
- CUET and UG Entrance
- Judiciary Exams
- Regulatory Body Exams
- Software Development