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In a D flip-flop output Q = Input D when :

(a) The output is low
(b) The output is high
(c) Clock is enabled
(d) Both reset and set input disabled

  • A.(c)
  • B.(a) and (b)
  • C.(a) and (c)
  • D.(c) and (d)

Answer: D

The keyed answer is (c) and (d).

A D flip-flop copies its D input to Q on the active clock edge, so the clock must be enabled (c). Most practical D flip-flops also have asynchronous preset (set) and clear (reset) inputs, which override the clock; Q follows D only while both of these are inactive (d).

The present state of the output, low (a) or high (b), has no bearing on whether D is transferred: the D flip-flop has no state-dependent input behaviour, unlike JK toggling. So the options including (a) or (b) are wrong, and (c) alone omits the condition on preset and clear.

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