Discussion
Consider a computer with a 4 MHz processor. Its DMA controller can transfer 8 bytes in 1 cycle from a device to main memory through cycle stealing at regular intervals. Which one of the following is the data transfer rate (in bits per second) of the DMA controller if 1% of the processor cycles are used for DMA?
Answer: C
The transfer rate is 25,60,000 bits per second.
The processor has \(4 \times 10^{6}\) cycles per second, and 1% of them, 40,000 cycles, go to DMA. Each stolen cycle moves 8 bytes:
\[ \begin{aligned} 40000 \times 8 &= 320000\ \text{bytes/s} \\ 320000 \times 8 &= 2560000\ \text{bits/s} \end{aligned} \]
That is 2.56 million bits per second, written 25,60,000 in the Indian grouping.
2,56,000 is ten times too small, and 3,200 and 32,000 are far smaller still, though 40,000 transfers of 64 bits each happen every second.
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