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Consider the following circuit:

Logic circuit: P drives a two-input NAND gate with both inputs tied together, Q drives another such NAND gate, and their outputs feed a third NAND gate whose output is Y

Suppose the input signal P is

Signal P: two pulses from 0 V to +5 V early in the time window, then 0 V

and the input signal Q is

Signal Q: 0 V until one pulse to +5 V later in the time window, after both pulses of P

Which one of the following output signals is correct?

  • A.Output Y against t: three pulses to +5 V
  • B.Output Y against t: two pulses to +5 V
  • C.Output Y against t: 0 V throughout
  • D.Output Y against t: one long pulse at +5 V

Answer: A

The output is three pulses (A).

A NAND gate with both inputs tied together is an inverter, so the first two gates give P′ and Q′. The final NAND gives

\[ Y = (P' \cdot Q')' = P + Q \]

by De Morgan's law. So Y is high whenever P or Q is high. P has two pulses early on and Q one pulse later, at a time when P is low, so Y shows all three pulses.

Two pulses (B) would be P alone, ignoring Q. A flat zero (C) is P AND Q, which is never high since the pulses do not overlap. One long pulse (D) does not follow from any combination of these inputs.

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