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In a 2-to-1 multiplexer as shown below, the output X = A0 if C = 0, and X = A1 if C = 1.

(Figure: a block with data inputs A0 and A1, select input C and output X.)

Which one of the following is the correct implementation of this multiplexer?

  • A.Circuit: A0 into an AND gate with C inverted at its other input, A1 into an AND gate with C, and both AND outputs into an OR gate giving X
  • B.Circuit: A0 into an AND gate with C, A1 into an AND gate with C inverted at its other input, and both AND outputs into an OR gate giving X
  • C.Circuit: A0 into an OR gate with C inverted at its other input, A1 into an OR gate with C, and both OR outputs into an OR gate giving X
  • D.Circuit: A0 into an AND gate with C, A1 into an AND gate with C, no inverter, and both AND outputs into an OR gate giving X

Answer: A

The correct implementation is circuit (A).

A 2-to-1 multiplexer computes

\[ X = A_{0}\bar{C} + A_{1}C \]

so one AND gate must pass \(A_{0}\) when \(C = 0\), which needs \(C\) inverted at that gate, and the other must pass \(A_{1}\) when \(C = 1\), with \(C\) uninverted. An OR gate combines them. Circuit (A) has the inversion bubble on the \(C\) input of the \(A_{0}\) gate: exactly this.

Circuit (B) inverts \(C\) at the \(A_{1}\) gate, so it selects \(A_{1}\) when \(C = 0\), the reverse of the specification. Circuit (D) has no inversion, so both gates are enabled together by \(C = 1\) and both disabled by \(C = 0\). Circuit (C) uses OR gates in the first stage, which pass a 1 whenever either input is 1, so it cannot select one input.

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