Discussion
An instruction format has the following structure:
Instruction Number: Opcode destination reg, source reg-1, source reg-2
Consider the following sequence of instructions to be executed in a pipelined processor:
I1: DIV R3, R1, R2
I2: SUB R5, R3, R4
I3: ADD R3, R5, R6
I4: MUL R7, R3, R8
Which of the following statements is/are TRUE?
Answer: A
Only the first statement is true: There is a RAW dependency on R3 between I1 and I2.
I1 writes R3 and I2 then reads R3, so I2 must wait for I1's result: a read-after-write (true) dependency.
The other three name the wrong kind of hazard. Between I1 and I3 both instructions write R3, which is write-after-write (WAW), not WAR. Between I2 and I3, I2 reads R3 and I3 later writes it, which is write-after-read (WAR), not RAW. Between I3 and I4, I3 writes R3 and I4 reads it, which is RAW, not WAW.
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