Discussion
An engineer reports a context switch time of 3 ns on a 100 MHz core. The proper response is
Answer: A
Correct answer: the figure is impossible, one cycle being 10 ns
At 100 MHz a single clock cycle is 10 nanoseconds, and a context switch saves and restores a register set - tens of cycles at best. Three nanoseconds is less than one cycle, so the figure cannot be right whatever the kernel does. Checking a claim against the clock period is the quickest test available.
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