Discussion
Assertion (A) : In order to synchronise a Mealy type circuits the inputs of the sequential circuit must be synchronized with the clock and the outputs must be sampled only during the clock edge.
Reason (R) : In Mealy model the outputs may change if input changes during the clock period and output may have momentary false values.
Answer: A
The answer is both (A) and (R) are true and (R) is the correct explanation of (A).
In a Mealy machine the outputs depend on the present state and the present inputs. If an input changes in the middle of a clock period, the output can change at once and may pass through momentary false values (glitches) before settling, which is what R says.
That is precisely why A is required: to get clean synchronous behaviour, the inputs are synchronised with the clock and the outputs are read only at the clock edge, when they are guaranteed to be valid. A Moore machine avoids the problem because its outputs depend on the state alone.
Post your comment
Please log in or register to post a comment.
Examination Categories
- SSC Exams
- Banking Exams
- Teaching Exams
- Civil Services Exams
- Railways Exams
- Engineering Recruitment Exams
- Defence Exams
- State Government Exams
- Police Exams
- Insurance Exams
- Nursing Exams
- Other Government Exams
- NRA CET
- PG Entrance Exams
- Campus Placement
- MBA Entrance Exams
- CUET and UG Entrance
- Judiciary Exams
- Regulatory Body Exams
- Software Development