Your Answer : (Not Answered)

Correct Answer : C

The statement that is not a characteristic of NUMA machines is (iii), access to remote memory is faster than access to local memory.

NUMA (non-uniform memory access) multiprocessors have three key characteristics: a single address space visible to all CPUs (i); access to remote memory through ordinary LOAD and STORE instructions (ii); and access to remote memory that is slower than access to local memory (iv). The non-uniformity is precisely that local memory is faster.

Statement (iii) contradicts (iv) and the very idea of NUMA, so it is the odd one out; the other three are true.

Your Answer : (Not Answered)

Correct Answer : A

The average access time is 157.5 nano sec.

Reads: a hit takes the cache time, 50 ns; on a miss the cache is checked and then main memory is read, 50 + 300 = 350 ns. Writes: with write-through, every write goes to main memory, 300 ns.

\[ \begin{aligned} t_{read} &= 0.8(50) + 0.2(350) = 110 \\ t &= 0.75(110) + 0.25(300) \\ &= 82.5 + 75 = 157.5\ \text{ns} \end{aligned} \]

110 ns is the read time alone and 82.5 ns is the read share only, both ignoring the writes; 75 ns is just the write share.

Your Answer : (Not Answered)

Correct Answer : D

Strobe and handshaking solve the problems of Asynchronous I/O synchronization.

When the CPU and an I/O device run on independent clocks, the transfer is asynchronous, and the receiver has no common clock to tell it when valid data is on the bus. Control signals have to coordinate the timing. In the strobe method one unit pulses a strobe line to say when data is valid. In handshaking, a second control line lets the receiver acknowledge that it has taken the data, so each step is confirmed.

The problem these mechanisms address is therefore timing coordination, synchronisation, in asynchronous transfer. Synchronous transfer needs neither, because both units share a clock.

Your Answer : (Not Answered)

Correct Answer : D

All three are memory performance parameters, so the answer is (i), (ii) and (iii).

William Stallings gives three performance parameters for memory: access time (latency), the time to perform a read or write; memory cycle time, the access time plus any further time before a second access can start; and transfer rate, the rate at which data can be moved into or out of the memory unit.

Each option that leaves one of them out is therefore incomplete.

Your Answer : (Not Answered)

Correct Answer : C

CB2H - 972H = 340H.

In 16's complement subtraction, add the 16's complement of the subtrahend and discard the end carry. The 15's complement of 972 is FFF - 972 = 68D; adding 1 gives the 16's complement 68E.

\[ \begin{aligned} \text{CB2} + \text{68E} &= \text{1340} \\ \text{discard carry} &\Rightarrow \text{340H} \end{aligned} \]

Check in decimal: CB2H = 3250, 972H = 2418, and 3250 - 2418 = 832 = 340H. 68DH is only the 15's complement of the subtrahend, and 1340H is the sum before the end carry is dropped.

Your Answer : (Not Answered)

Correct Answer : D

The result is \(-\ \text{579}_{H}\).

In 15's complement subtraction, add the 15's complement of the subtrahend. The 15's complement of C14 is found by subtracting each digit from F: F - C = 3, F - 1 = E, F - 4 = B, giving 3EB.

\[ \begin{aligned} \text{69B} + \text{3EB} &= \text{A86} \\ \text{end carry} &= \text{none} \end{aligned} \]

With no end-around carry, the result is negative and in complement form. Its magnitude is the 15's complement of A86: F - A = 5, F - 8 = 7, F - 6 = 9, so the answer is -579 hexadecimal. Check: C14 - 69B = 579.

3EB is only the complement of C14, A86 is the uncorrected sum, and 579 without the sign is the magnitude, so all three miss the sign or the final step.

Your Answer : (Not Answered)

Correct Answer : A

Only the first statement is true: There is a RAW dependency on R3 between I1 and I2.

I1 writes R3 and I2 then reads R3, so I2 must wait for I1's result: a read-after-write (true) dependency.

The other three name the wrong kind of hazard. Between I1 and I3 both instructions write R3, which is write-after-write (WAW), not WAR. Between I2 and I3, I2 reads R3 and I3 later writes it, which is write-after-read (WAR), not RAW. Between I3 and I4, I3 writes R3 and I4 reads it, which is RAW, not WAW.

Your Answer : (Not Answered)

Correct Answer : B

The dependence that causes a data hazard is Read-after-write.

In a read-after-write (true) dependence, a later instruction reads a register that an earlier instruction writes. In a pipeline the later instruction can reach its operand-read stage before the earlier one has written its result back, so it would read a stale value unless the pipeline stalls or forwards the result.

Read-after-read never causes a hazard, because reading does not change the register. Write-after-read and write-after-write are name dependences: in the standard in-order pipeline, where every instruction reads early and writes in the last stage in program order, they cannot go wrong. They become hazards only in pipelines that let instructions complete out of order, where register renaming removes them.

Your Answer : (Not Answered)

Correct Answer : B

The correct matching is P-4, Q-2, R-1, S-3.

• Immediate: the operand is in the instruction itself, which is how a constant is supplied (4).
• Indirect: the instruction names a location that holds the address of the operand, which is how a pointer is followed (2).
• Base with index: a base register holds the start of an array and an index register selects the element, so the address varies at run time (1).
• Base with offset/displacement: a base register holds the start of a record and a fixed offset in the instruction selects the field (3).

Options that pair indirect addressing with a record element, or immediate addressing with an array, mix up the fixed offset of a record field with the variable index of an array element.

Your Answer : (Not Answered)

Correct Answer : D

All three are RISC characteristics, so the answer is I, II and III.

A RISC processor is a load-store machine: arithmetic works only on registers, and memory is reached only by load and store instructions (I). Its instructions have a fixed length, usually one word, which makes fetching and decoding simple and pipelining easy (II). With a small set of simple instructions, the control unit can be hardwired rather than microprogrammed, which is faster (III).

Each two-item option leaves out one of these, so none of them is complete. Variable-length instructions, memory operands in arithmetic and microprogrammed control are the CISC features they contrast with.

Your Answer : (Not Answered)

Correct Answer : B

The tag field has \(P - N + \log_{2} K\) bits.

The physical address has \(P\) bits. A block is \(2^{M}\) words of \(2^{W}\) bytes, so the block offset is \(M + W\) bits. The cache holds \(2^{N} / 2^{M+W}\) blocks, grouped \(K\) to a set:

\[ \begin{aligned} \text{sets} &= 2^{N - M - W} / K \\ \text{index} &= N - M - W - \log_{2} K \\ \text{tag} &= P - \text{index} - (M + W) \\ &= P - N + \log_{2} K \end{aligned} \]

Check: a direct-mapped cache (\(K = 1\)) gives a tag of \(P - N\) bits, and higher associativity means fewer sets and so a longer tag. \(P - N - \log_{2} K\) gets that direction wrong, and the options with \(- M - W\) subtract the block offset twice.

Your Answer : (Not Answered)

Correct Answer : A

The correct order is QPTRS.

1. (Q) The processor finishes the instruction it is executing; interrupts are checked between instructions.
2. (P) It saves the status of process L on the control stack, so L can be resumed.
3. (T) It loads the PC with the address of the interrupt service routine.
4. (R) It runs the interrupt service routine.
5. (S) It restores L's status from the stack and L continues.

PTRSQ saves the status before the current instruction completes, TRPQS jumps to the handler without first saving L's state, and QTPRS loads the new PC before saving the old state, which would lose L's return address.

Your Answer : (Not Answered)

Correct Answer : C

S1 is true and S2 is false.

S1: In a vectored interrupt scheme, the interrupting device supplies a vector that points the CPU straight at its service routine. In a non-vectored scheme, the CPU jumps to a fixed location and must then find out which device interrupted, usually by polling, before reaching the right ISR. So starting the ISR typically takes longer, and S1 is true.

S2: Daisy chaining is a hardware priority scheme. The interrupt-acknowledge signal passes from device to device along the chain, and the first requesting device stops it and places its identifying vector on the bus. The CPU does not poll each device; that describes software polling. So S2 is false.

Your Answer : (Not Answered)

Correct Answer : C

The transfer rate is 25,60,000 bits per second.

The processor has \(4 \times 10^{6}\) cycles per second, and 1% of them, 40,000 cycles, go to DMA. Each stolen cycle moves 8 bytes:

\[ \begin{aligned} 40000 \times 8 &= 320000\ \text{bytes/s} \\ 320000 \times 8 &= 2560000\ \text{bits/s} \end{aligned} \]

That is 2.56 million bits per second, written 25,60,000 in the Indian grouping.

2,56,000 is ten times too small, and 3,200 and 32,000 are far smaller still, though 40,000 transfers of 64 bits each happen every second.

Your Answer : (Not Answered)

Correct Answer : C

The product is 0xC15C2EF4.

Decode P: 0xC1800000 is sign 1, exponent 1000 0011 = 131, fraction 0, so \(P = -1.0 \times 2^{131-127} = -16 = -2^{4}\).

Multiplying by \(-2^{4}\) flips the sign and adds 4 to the exponent, leaving the significand unchanged. Q = 0x3F5C2EF4 is sign 0, exponent 0111 1110 = 126, and some fraction f. Then:

\[ \begin{aligned} \text{sign} &= 1,\quad \text{exponent} = 126 + 4 = 130 \\ 130 &= 1000\,0010_{2} \\ \text{bits} &= 1\ 10000010\ f \end{aligned} \]

The leading nine bits 1 1000 0010 followed by the unchanged fraction read as 0xC15C2EF4 (about \(-13.76\), which is \(-16 \times 0.86\)). 0x405C2EF4 and 0x404C2EF4 have a positive sign, and 0xC14C2EF4 alters the fraction bits, which multiplication by a power of two never does.

Your Answer : (Not Answered)

Correct Answer : B

The false statement is \(C = A + B\).

Decode each register as sign, 8-bit exponent with bias 127, and 23-bit fraction with a hidden leading 1.

• 0xC1400000 = 1 10000010 1000...: sign negative, exponent \(130 - 127 = 3\), significand 1.1 in binary = 1.5, so \(A = -1.5 \times 8 = -12\).
• 0x42100000 = 0 10000100 0010...: exponent \(132 - 127 = 5\), significand 1.001 in binary = 1.125, so \(B = 1.125 \times 32 = 36\).
• 0x41400000 = 0 10000010 1000...: exponent 3, significand 1.5, so \(C = 12\).

Then \(A + C = -12 + 12 = 0\), \(B = 36 = 3C\) and \(B - C = 24 \gt 0\) are all true, while \(A + B = -12 + 36 = 24\), which is not 12. So \(C = A + B\) is the false statement.

Your Answer : (Not Answered)

Correct Answer : B

Overflow occurs for R1 = 1100 and R2 = 1010.

In 4-bit two's complement the range is −8 to 7. Overflow happens when two numbers of the same sign give a result outside that range, which shows as a result with the opposite sign.

1100 is −4 and 1010 is −6. Their sum is −10, below −8; the 4-bit result is 0110, a positive number, so the addition overflows.

The others stay in range: 1011 + 1110 is −5 + (−2) = −7; 0011 + 0100 is 3 + 4 = 7; 1001 + 1111 is −7 + (−1) = −8, the most negative value, still representable.

Your Answer : (Not Answered)

Correct Answer : B

The largest number is 0 1111 1110 1111 1111 1111 1111 1111 111.

All four have sign bit 0, so they are positive, and a larger exponent field gives a larger number. The exponent 1111 1111 is reserved: with a non-zero mantissa it encodes NaN (not a number), so the third pattern is not a number at all and cannot be the largest.

The largest usable exponent is 1111 1110 (254, an actual exponent of 127), and with an all-ones mantissa this pattern is the largest finite single-precision value, about \(3.4 \times 10^{38}\).

The first and fourth patterns have exponent 0111 1111 (127, an actual exponent of 0), giving values just under 2 and exactly 1.

Your Answer : (Not Answered)

Correct Answer : B

The addition time is \(\Theta(\log(n))\).

A carry lookahead adder computes generate and propagate signals for every bit pair, then combines them to find all the carries at once instead of rippling. Each carry \(c_{i}\) is an AND-OR expression over up to \(i\) generate and propagate terms. With gates of fan-in at most two, an AND or OR of \(n\) inputs must be built as a balanced tree of depth \(\log_{2} n\), and the prefix structure of the carry computation also has logarithmic depth. So the delay grows as \(\Theta(\log n)\).

\(\Theta(1)\) would need unbounded fan-in. \(\Theta(n)\) is the ripple-carry adder, which carry lookahead is designed to beat, and \(\Theta(\sqrt{n})\) is typical of carry-skip or carry-select designs, not full lookahead.

Your Answer : (Not Answered)

Correct Answer : B

Statement i is false and statements ii, iii and iv are true. A compiler translates the whole source program at once into machine code, and it is an interpreter that works line by line, so statement i is wrong. Computer architecture means the attributes of a system visible to the programmer. RISC cuts the cycles per instruction at the cost of more instructions per program, and the arithmetic and logical work is done by the ALU under the control unit. So i-False, ii-True, iii-True and iv-True is correct.