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Embedded Systems [ Question No: 1 To 20 ] :
Bringing up peripherals one at a time rather than all together is worth the effort because
A serial link works at 9600 baud and produces framing errors at 115 200. The likeliest cause is
Match the bus with its distinguishing feature.
1. I2C 2. SPI 3. CAN
P. Differential pair with non-destructive arbitration Q. Two wires with addressing and acknowledgement R. Full duplex with a select line per device
Match the driver style with when it suits.
1. Polled 2. Interrupt-driven 3. DMA-driven
P. High continuous data rate Q. Short wait during initialisation R. Occasional events at unpredictable times
A driver buffers incoming data chiefly because
A reserved field is included in a register structure in order to
Assertion: a queue is preferable to shared memory with a lock. Reason: the queue confines the shared state to the kernel, where it is already protected.
The number of times a 4 ms task is released within a 15 ms window is at most
Consider the following statements about scheduling.
1. A utilisation above unity is always infeasible 2. The rate monotonic bound is necessary and sufficient 3. Earliest deadline first is optimal on one processor
Context switch overhead is accounted for in a schedulability analysis by
A design has 200 tasks on a part with 32 kB of RAM. The immediate concern is
A task and an interrupt handler share a 32-bit counter on an 8-bit core. Reading it in the task requires
A selection is revisited two years later because the part has been discontinued. The document that makes the replacement quick is
A safety-related product to IEC 61508 needs a microcontroller with
Moving from an 8-bit to a 32-bit core often reduces code size for arithmetic-heavy work because
The criterion that most often eliminates candidates before any other is
Match the block with its function.
1. Watchdog timer 2. DMA controller 3. Interrupt vector table
P. Holds the handler addresses Q. Resets a hung system R. Moves data without the core
A digital signal processor is distinguished from a general purpose core by
Which memory type retains its contents without power and can be erased electrically in blocks?
The von Neumann organisation is distinguished by
Total number of questions : 20
Number of answered questions : 0
Number of unanswered questions : 20
Embedded Systems [ Question No: 1 To 20 ] :
Bringing up peripherals one at a time rather than all together is worth the effort because
Your Answer : (Not Answered)
Correct Answer : D
Correct answer: a fault is then attributable to the one thing just changed
Bringing up one peripheral at a time keeps the number of possible causes at one. Enable six at once and a failure could come from any of them or from an interaction, and the search space is far larger than six. It is the same discipline as changing one variable at a time in an experiment, and it costs less time than it appears to.
A serial link works at 9600 baud and produces framing errors at 115 200. The likeliest cause is
Your Answer : (Not Answered)
Correct Answer : C
A percentage error that is tolerable at a low rate is often generated by a divider that cannot express the higher rate exactly, particularly from an untrimmed internal oscillator. A parity mismatch would fail at both speeds and a small buffer gives overruns rather than framing errors.
Match the bus with its distinguishing feature.
1. I2C 2. SPI 3. CAN
P. Differential pair with non-destructive arbitration Q. Two wires with addressing and acknowledgement R. Full duplex with a select line per device
Your Answer : (Not Answered)
Correct Answer : A
Correct answer: 1-Q, 2-R, 3-P
Three buses, three quite different designs. I2C is two shared wires with addressing in the protocol and an acknowledgement per byte. SPI is full duplex with a separate select line for each device and no addressing at all. CAN uses a differential pair with non-destructive arbitration, so the highest-priority message wins the bus without any message being lost or corrupted.
Match the driver style with when it suits.
1. Polled 2. Interrupt-driven 3. DMA-driven
P. High continuous data rate Q. Short wait during initialisation R. Occasional events at unpredictable times
Your Answer : (Not Answered)
Correct Answer : D
The three styles form a progression in both capability and complexity, and the right choice follows from the rate and the predictability of the arrivals. Using the wrong one wastes either processor time or engineering effort.
A driver buffers incoming data chiefly because
Your Answer : (Not Answered)
Correct Answer : C
Data arrives when the device chooses and is read when the application gets round to it, so something must hold it in between. How much is needed follows from the arrival rate and the longest the consumer may be delayed.
A reserved field is included in a register structure in order to
Your Answer : (Not Answered)
Correct Answer : A
Correct answer: keep the following members at their correct offsets
A peripheral’s registers sit at fixed addresses, and gaps in the map must be represented or every member after the gap lands on the wrong register. A reserved field fills the gap so the structure’s offsets match the hardware exactly, which is the whole point of overlaying a structure on a peripheral.
Assertion: a queue is preferable to shared memory with a lock. Reason: the queue confines the shared state to the kernel, where it is already protected.
Your Answer : (Not Answered)
Correct Answer : A
Handing an item over and forgetting it removes every opportunity for a race, whereas shared memory leaves the discipline to every future maintainer. That confinement of the shared state is precisely why the queue is the safer structure.
The number of times a 4 ms task is released within a 15 ms window is at most
Your Answer : (Not Answered)
Correct Answer : D
The ceiling of fifteen over four is four, which is the figure that enters a response time recurrence as the interference count. Taking the floor instead, and getting three, understates the interference and is the commonest arithmetic error in the analysis.
Consider the following statements about scheduling.
1. A utilisation above unity is always infeasible 2. The rate monotonic bound is necessary and sufficient 3. Earliest deadline first is optimal on one processor
Your Answer : (Not Answered)
Correct Answer : D
Correct answer: 1 and 3 only are correct
Statements 1 and 3 are correct: utilisation above unity is infeasible for any algorithm, and earliest deadline first is optimal on one processor. Statement 2 overstates the rate monotonic bound, which is sufficient but not necessary - a set exceeding it may still meet every deadline, which is why response time analysis exists.
Context switch overhead is accounted for in a schedulability analysis by
Your Answer : (Not Answered)
Correct Answer : D
Two switches per release, one in and one out, are charged to the task being released, which keeps the analysis in its usual form. On a set with short periods and a slow switch the correction can be several per cent of the processor.
A design has 200 tasks on a part with 32 kB of RAM. The immediate concern is
Your Answer : (Not Answered)
Correct Answer : D
Correct answer: the total stack requirement of the tasks
Each task needs its own stack and its own control block, so 200 tasks consume a substantial part of 32 kB before a single buffer is allocated - a modest 128 bytes each would be 25 kB. The design almost certainly needs fewer tasks, which is the conclusion the arithmetic forces.
A task and an interrupt handler share a 32-bit counter on an 8-bit core. Reading it in the task requires
Your Answer : (Not Answered)
Correct Answer : C
Four separate byte reads can be interrupted between any two of them, and the handler may increment the counter across a carry, so the value assembled is one that never existed. On a 32-bit core an aligned word read would be atomic and no protection would be needed.
A selection is revisited two years later because the part has been discontinued. The document that makes the replacement quick is
Your Answer : (Not Answered)
Correct Answer : C
The matrix records what mattered and which alternatives nearly qualified, so the search starts from a shortlist rather than from nothing. The schematic and the code say what was built but not why, which is the question a replacement has to answer.
A safety-related product to IEC 61508 needs a microcontroller with
Your Answer : (Not Answered)
Correct Answer : C
The certification requires evidence about the part's failure modes and the diagnostics that detect them, which only the vendor can supply. Parts sold for such use come with a safety manual and often with a self-test library.
Moving from an 8-bit to a 32-bit core often reduces code size for arithmetic-heavy work because
Your Answer : (Not Answered)
Correct Answer : C
A 16-bit add on an 8-bit machine becomes several instructions with carry handling, and a 32-bit multiply becomes a library call. Doing it in one instruction saves both space and time, which often outweighs the wider instruction encoding.
The criterion that most often eliminates candidates before any other is
Your Answer : (Not Answered)
Correct Answer : C
Peripherals are a pass or fail test, whereas price, longevity and tools are matters of degree on which a compromise is possible. Adding an external device to make up a missing peripheral is always an option but usually a costly one.
Match the block with its function.
1. Watchdog timer 2. DMA controller 3. Interrupt vector table
P. Holds the handler addresses Q. Resets a hung system R. Moves data without the core
Your Answer : (Not Answered)
Correct Answer : C
Correct answer: 1-Q, 2-R, 3-P
Three independent blocks. The watchdog must be refreshed periodically by working software and resets the device if it is not, so it recovers a hung system. The DMA controller transfers data between memory and peripherals without the core, freeing it for other work. The interrupt vector table holds the addresses of the handlers, which the core reads when an interrupt is taken.
A digital signal processor is distinguished from a general purpose core by
Your Answer : (Not Answered)
Correct Answer : B
A single-cycle multiply-accumulate, circular addressing for delay lines and bit-reversed addressing for transforms are the characteristic features. Modern general purpose cores have absorbed much of this in their vector units, which has narrowed the gap considerably.
Which memory type retains its contents without power and can be erased electrically in blocks?
Your Answer : (Not Answered)
Correct Answer : C
Block erasure is the distinguishing feature: byte-erasable non-volatile memory is EEPROM, and flash trades byte granularity for much higher density. It is why program memory is flash and small calibration stores are often EEPROM.
The von Neumann organisation is distinguished by
Your Answer : (Not Answered)
Correct Answer : A
Sharing the path means an instruction fetch and a data access cannot happen in the same cycle, which is the von Neumann bottleneck. The Harvard organisation splits them and can do both at once, at the cost of more silicon and more pins.
Marks
Total number of questions : 20
Number of answered questions : 0
Number of unanswered questions : 20