Your Answer : (Not Answered)

Correct Answer : C

The passage lists cache, pipelining and branch prediction as features that improved performance, speed, memory and data transfer. Power consumption is not an enhanced feature of that kind, since it is a cost and not an improvement, and it is not listed among the advances. So pipelining, branch prediction and cache are enhanced features and power consumption is the odd one out. The answer is power consumption.

Your Answer : (Not Answered)

Correct Answer : B

After the wafer is coated with photoresist, it is exposed to UV radiation through a mask (2), the exposed or unexposed resist is dissolved in the developer (4), the oxide or metal not protected by the resist is etched (1), and the remaining resist is stripped (3). The order is 2, 4, 1, 3. The mask exposes the resist to UV light first, the developer then removes the soluble part of it to open windows, etching removes the exposed oxide through these windows, and only then is the leftover resist stripped, because the resist is needed as the protective layer during etching. The answer is 2, 4, 1, 3.

Your Answer : (Not Answered)

Correct Answer : C

FPGA programming is done using hardware description languages (HDLs) or schematic entry.

A designer describes the circuit in VHDL or Verilog, or draws it as a schematic. Vendor tools synthesise this into a netlist, map it onto the device's logic blocks, place and route it, and produce a configuration bitstream that is loaded into the FPGA.

Most FPGAs are SRAM-based, so they are reconfigurable as often as needed; only antifuse types are one-time programmable, so 'permanent' is wrong in general. The bitstream configures hardware rather than being machine code executed by a processor. And the devices are routinely reprogrammed in the field over JTAG or from flash memory, so no laboratory is required.

Your Answer : (Not Answered)

Correct Answer : A

Scalable design rules are given by lambda rules.

Mead and Conway's lambda-based rules express every layout dimension, such as minimum widths, spacings and overlaps, as a multiple of a single unit \(\lambda\), roughly half the minimum feature size. When the process shrinks, only the value of \(\lambda\) changes, and the same layout can be scaled to the new technology.

Micron rules give absolute dimensions in micrometres for one particular process, so they are more precise but not scalable. 'Layer rules' and 'thickness rules' are not names of a scalable rule system.

Your Answer : (Not Answered)

Correct Answer : B

The ratio is 4/1.

For an nMOS inverter with a depletion-mode pull-up, the pull-up to pull-down impedance ratio \(Z_{pu}/Z_{pd}\) must be at least 4:1 when the inverter is driven directly by another nMOS inverter, so that its output low is low enough and its switching threshold sits near the middle of the logic swing.

8/1 is the ratio needed when the inverter is driven through one or more pass transistors, because the pass transistor drops a threshold voltage and reduces the input high level. 8/3 and 1/4 are not the standard design ratios; 1/4 would invert the required relationship.

Your Answer : (Not Answered)

Correct Answer : A

The key gives Both (A) and (R) are true and (R) is the correct explanation of (A).

A stick diagram is a simple, quick way of drawing the circuit of a logic gate in a form close to its layout: each transistor, conductor and layer is shown as a coloured stick or line, without exact widths or spacings. It lets a designer plan the topology of a gate before drawing the full mask layout, which is the sense of statement A.

It is easy precisely because it uses sticks or lines to represent devices and conductors, as R says, so R explains A. The options calling either statement false are therefore wrong.

Your Answer : (Not Answered)

Correct Answer : C

The VHDL entity represents a component's external behaviour and interface.

A VHDL design unit has two parts. The entity declaration names the component and lists its ports (inputs, outputs and their types) and generics; it is what other designs see when they use the component, like a symbol or a pin-out. The architecture body describes what goes on inside, the internal behaviour or structure that implements the entity.

A port is a single connection point listed inside the entity, not the whole interface. A signal is an internal wire within an architecture. The architecture is the implementation, the opposite of the external view the question asks about.

Your Answer : (Not Answered)

Correct Answer : B

The masking chemical is silicon nitride.

In the LOCOS (local oxidation of silicon) process, a patterned layer of silicon nitride, Si₃N₄, covers the active areas where transistors will be built. Oxygen and water vapour diffuse through nitride extremely slowly, so the field oxide grows only in the exposed regions, isolating neighbouring devices.

Silver nitride is not used in silicon processing. Hydrofluoric acid etches silicon dioxide; it removes oxide rather than masking against its growth. Polysilicon is used for gates and as a buffer layer in some LOCOS variants, but it oxidises readily and is not the mask itself.

Your Answer : (Not Answered)

Correct Answer : D

The key gives Fabrication of p-MOS transistor requires few additional steps compared to n-MOS transistor.

In the common n-well CMOS process the starting wafer is p-type, so the nMOS transistors are built directly in the substrate. The pMOS transistors need an n-type region to sit in, which means extra steps: an n-well mask, the n-well implant and drive-in, and a separate p+ source/drain implant with its own mask. So the pMOS device is the one that costs additional processing.

The first option reverses this. The second is wrong because the two devices need different well and implant steps, and the third, while loosely true, does not identify the specific point the question tests.

Your Answer : (Not Answered)

Correct Answer : C

The correct matching is a-iv, b-iii, c-ii, d-i.

• Chemical analysis: EDAX (energy-dispersive X-ray analysis) identifies elements from their characteristic X-rays (iv).
• Structural characteristics: XRD (X-ray diffraction) reveals crystal structure and lattice spacing (iii).
• Topology: SEM (scanning electron microscope) images surface topography (ii).
• Electrical characteristics: a probe station makes electrical contact with devices on a wafer for I-V and C-V measurements (i).

The other codes swap XRD and SEM, or give chemical analysis to the probe station.

Your Answer : (Not Answered)

Correct Answer : C

Wet oxidation is Si + \(\mathrm{2H_2O}\).

In wet (steam) oxidation, silicon reacts with water vapour at about 900-1100 °C to form silicon dioxide and release hydrogen:

\[ \mathrm{Si + 2H_2O \rightarrow SiO_2 + 2H_2} \]

It grows oxide much faster than dry oxidation and is used for thick field oxides. Si + \(\mathrm{O_2}\) is dry oxidation, which grows a slower, denser oxide used for gate oxides. HF does not oxidise silicon; it etches silicon dioxide. Hydrogen does not form an oxide at all.

Your Answer : (Not Answered)

Correct Answer : B

The order is (1), (2), (3), (4): illumination diffuser, condenser lens, reticle, interferometer.

In an optical stepper, light from the source first passes through the illumination diffuser, which spreads it uniformly. The condenser lens then collects the light and directs it evenly onto the reticle (printed 'Reficle' in the paper), the mask carrying the pattern of one or a few dies. Projection optics image the reticle onto the wafer, whose stage position is measured by a laser interferometer so that each die is exposed in exactly the right place.

The other options put the reticle before the condenser, or start with the interferometer, which belongs to the wafer stage at the end of the path, not at the light source.

Your Answer : (Not Answered)

Correct Answer : A

The device is the DLL (delay-locked loop).

FPGAs include delay-locked loops (and later digital clock managers built around them) to remove clock skew. A DLL compares the clock arriving at the logic with the incoming clock and inserts just enough delay to align them, so that every flip-flop on the chip sees its clock edge at the same time; it can also multiply, divide or shift the clock phase.

The CLB (configurable logic block) holds the look-up tables and flip-flops, the IOB (input/output block) interfaces the pins, and JTAG is the boundary-scan test and programming interface. None of them synchronises the clock.

Your Answer : (Not Answered)

Correct Answer : D

The n and p transistors are separated by a dotted brown line.

In the colour code used for CMOS stick diagrams (as in Pucknell and Eshraghian's Basic VLSI Design), the n-well or demarcation line that divides the region of n-transistors from the region of p-transistors is drawn in brown.

The other colours have their own meanings in the same scheme: blue is metal, yellow is p-diffusion, and black marks contact cuts. None of them is the demarcation line.

Your Answer : (Not Answered)

Correct Answer : D

The n-channel device is preferred because the electron mobility in Si is larger than the mobility of holes.

In silicon, electrons have a mobility of about 1350 cm\(^{2}\)/V·s and holes about 480 cm\(^{2}\)/V·s. Since drain current is proportional to carrier mobility, an n-channel MOSFET of the same size carries two to three times the current, switches faster and has a lower on-resistance than a p-channel device.

Input impedance is not the reason: in both types the gate is insulated by oxide, so both have extremely high input impedance. The option saying electron mobility is smaller than hole mobility states the fact the wrong way round.

Your Answer : (Not Answered)

Correct Answer : B

The N-channel MOSFET is better because it is faster.

In an N-channel device the current is carried by electrons, whose mobility in silicon (about 1350 cm²/V s) is roughly two to three times the hole mobility (about 480 cm²/V s) that governs a P-channel device. For the same size, an NMOS transistor therefore has higher transconductance and lower on-resistance, so it charges load capacitance faster and switches faster.

Noise immunity is a property of the logic family's voltage levels, not of the channel type. TTL compatibility and drive capability depend on the circuit design and supply voltages, so they are not the defining advantage of N-channel over P-channel devices.

Your Answer : (Not Answered)

Correct Answer : B

The gate material could be polysilicon.

Heavily doped polycrystalline silicon replaced aluminium as the standard MOS gate material in the 1970s. It withstands the high-temperature steps after gate formation, which allows the self-aligned gate process in which the gate itself masks the source and drain implants, and its doping can be chosen to set the threshold voltage. Advanced processes have since moved to metal gates with high-k dielectrics.

Single-crystal silicon is the substrate, not the gate. Boron and phosphorus are dopants used to make p-type and n-type regions; they are not gate electrode materials themselves.

Your Answer : (Not Answered)

Correct Answer : D

The material that cannot be used as the gate electrode is hafnium dioxide.

The gate electrode must be a conductor. Aluminium was the original gate metal, tungsten and other refractory metals are used in metal gate stacks, and gold, though rarely used in silicon processing because it contaminates silicon, is a conductor that can serve as a gate in experimental and compound-semiconductor devices.

Hafnium dioxide (HfO₂) is an insulator. It is used in modern high-k metal gate transistors as the gate dielectric, the layer under the electrode, precisely because it does not conduct, so it cannot be the gate electrode itself.

Your Answer : (Not Answered)

Correct Answer : D

The correct matching is a-ii, b-i, c-iv, d-iii.

• (a) The gate conductor of MOS transistors is usually doped polysilicon (ii).
• (b) A patterned SiO₂ layer masks the silicon against impurity diffusion (i).
• (c) Devices are isolated by local oxidation of silicon (LOCOS) or trench isolation (iv).
• (d) Layout is planned with stick diagrams, which show the layers and their connections before exact geometry is drawn (iii).

The other codes place the oxide mask, the stick diagram or the isolation method against the wrong item.

Your Answer : (Not Answered)

Correct Answer : C

The answer is (A) is true but (R) is false.

The Assertion is the standard definition: epitaxy is the deposition of a crystalline overlayer on a crystalline substrate, the layer following the substrate's crystal structure and orientation.

The Reason is false. One of the main advantages of epitaxy is that the layer can be doped during growth, by adding a dopant gas such as phosphine (PH₃), arsine or diborane to the reactor. This in-situ doping lets a lightly doped layer be grown on a heavily doped substrate, as for the collector of a bipolar transistor.