A shift register moves bits along one place per clock, which converts a parallel word into a serial stream, so A goes with 3. A multiplexer connects one of many inputs to a single output, which is a many-to-one switch, so B goes with 4. A decoder turns a binary code into an activated line, which is a form of code conversion, so C goes with 1.
A full-adder is a logic circuit which can add two single order bits plus a carry in from a previous adder. Its incomplete truth table is given in the table below. The missing entry in the outputs for SUM and CARRY out are
For \(A=1, B=1, C_{in}=1\) the three inputs total three. The sum bit is the total modulo 2, which is 1, and the carry out is 1 because the total is 2 or more. In XOR terms, \( 1\oplus 1\oplus 1 = 1 \), and the carry is the majority of the three inputs.
CMOS draws current essentially only while switching, so its static power dissipation is negligible - far below TTL or ECL - and its simple structure gives a low cost per gate. That combination is why CMOS displaced the other families.
NOR and NAND are the two universal gates: either alone can build NOT, AND and OR, and therefore any Boolean function. AND, OR and XOR cannot produce a complement by themselves.
The dual of an expression is formed by exchanging AND with OR and 0 with 1, leaving the variables uncomplemented. Applying that to \( x + yz \) turns the outer OR into AND and the inner AND into OR, giving \( x(y+z) \). Complementing the variables would give the complement, not the dual.
A D flip-flop transfers its input to its output at the clock edge, so its characteristic equation is \( Q_{next} = D \). It is the simplest of the flip-flops precisely because the next state does not depend on the present one.
Each of the four first-level multiplexers selects one of four inputs, giving sixteen inputs in all, and the final multiplexer chooses among their four outputs. Two select lines are needed at each level, four in total, which is right for \( 2^4 = 16 \) inputs.
Holding one input of an AND or NAND gate LOW forces the AND function to 0, which blocks the signal on the other input. If the output is then HIGH, the gate must be inverting the blocked 0 - so it is a NAND.
