Computer Network Questions and Answers

Answer: D

The key's answer is Network Server.

In a network, servers are named by the service they provide: a file server stores and shares files, a print server manages shared printers, and an application server runs applications for clients. These are standard server types.

'Network server' is only a general description of any server connected to a network, not a distinct type of server providing a particular service, which is why the key treats it as the one that is not a server type.

Answer: D

The topology that is not common is the Grid.

The common network topologies are bus (all devices on one shared cable), star (all devices joined to a central hub or switch), ring (each device connected to the next in a closed loop), and mesh, tree and hybrid forms.

A grid arrangement of links is used in some specialised systems, such as interconnects inside supercomputers, but it is not one of the common topologies of ordinary networks. Bus, star and ring are all standard ones.

Answer: C

The toolkit for building grids is the Globus toolkit.

The Globus Toolkit is open-source software for grid computing. It provides the services needed to share computing power and data across institutions: security, resource management, data transfer (GridFTP) and information services.

Apache Hadoop is a framework for distributed storage and processing of big data on clusters. Microsoft Azure is a commercial cloud computing platform. Microsoft Word is a word processor. None of them is a grid-building toolkit.

Answer: B

Computers communicate on the internet through TCP/IP.

TCP/IP is the protocol suite on which the internet runs. IP (Internet Protocol) gives every device an address and routes packets between networks, and TCP (Transmission Control Protocol) breaks data into packets and delivers them reliably and in order.

IP alone is only one layer of that suite. HTTPS is one application protocol, for secure web pages, and a web browser is a program that uses these protocols, not the means of communication itself.

Answer: C

The key's answer is a 32-bit number.

An IPv4 address, the classic internet address, is 32 bits long. It is written as four 8-bit numbers in dotted decimal form, such as 192.168.1.1, giving about 4.3 billion possible addresses.

8 and 16 bits are far too small; 8 bits is just one part of the dotted address. The newer IPv6 addresses are 128 bits long, but the question refers to the familiar IPv4 address.

Answer: B

Correct answer: True

The statement is true. The NOT gate, or inverter, has a single input and produces its complement: 0 becomes 1 and 1 becomes 0. Its Boolean expression is \( Y = \bar{A} \). It is the only basic gate with one input; every other takes two or more. On a diagram it is drawn as a triangle with a small circle at the output, and that circle - the bubble - is the general symbol for inversion, which is why NAND is drawn as AND with a bubble and NOR as OR with one. Two inverters in series cancel, giving \( \bar{\bar{A}} = A \), which is the involution law of Boolean algebra. Pairs of inverters are nevertheless used deliberately as buffers, to restore signal strength without changing the logic. An inverter is easily made from either universal gate by tying the inputs together: a NAND or a NOR with both inputs joined behaves exactly as a NOT.

Answer: B

Correct answer: baseband signal

The signal as it comes from the source, before it is modulated onto a carrier, is the baseband signal. The carrier is what it is later imposed on.

Answer: C

Correct answer: both inputs are HIGH

A NAND gate is an AND gate followed by an inverter, so its output is the complement of AND. AND gives 1 only when both inputs are 1; NAND therefore gives 0 only in that single case and 1 in the other three. Its truth table is worth holding in mind: 0,0 gives 1; 0,1 gives 1; 1,0 gives 1; 1,1 gives 0. NAND is called a universal gate because every other logic function can be built from it alone. An inverter is a NAND with both inputs tied together; an AND is a NAND followed by another NAND acting as an inverter; an OR is a NAND fed by two inverting NANDs, which is De Morgan’s theorem in hardware. NOR is universal for the same reason. That property matters in practice, since a manufacturer can build an entire logic family from one repeated cell.

Answer: A

Correct answer: is faster than main memory and holds recently used data

Cache is a small, very fast memory placed between the processor and main memory, holding copies of data and instructions that have recently been used or are likely to be used next. It works because of the principle of locality. Temporal locality means a location just accessed is likely to be accessed again soon; spatial locality means nearby locations are likely to be accessed next, which is why data is fetched in whole cache lines rather than single bytes. A request found in cache is a hit and is served in a few processor cycles; a miss requires main memory and costs hundreds. Because hit rates in practice exceed 90 per cent, the average access time approaches that of the cache. It is built from SRAM, which uses a flip-flop per bit and needs no refreshing, unlike the DRAM of main memory - faster but far more expensive per bit, which is why cache is small. Modern processors use several levels, L1 through L3.

Answer: B

Correct answer: the time between an input change and the corresponding output change

Propagation delay is the time taken for a change at the input to appear at the output. It is measured between the 50 per cent points of the two transitions, and it is usually quoted separately for a low-to-high and a high-to-low transition, since the two are rarely equal. It is the fundamental limit on clock speed. The longest chain of gates between two flip-flops - the critical path - must settle within one clock period, so the maximum frequency is the reciprocal of that total delay plus the flip-flop’s own setup time. It is also why a ripple counter is slower than a synchronous one: each stage waits for the one below it, and the delays accumulate. The fourth option describes fan-out, the number of gate inputs a single output can drive, which is a different specification and is itself limited by current and by the loading capacitance that increases the delay.