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Avionics Data Buses Questions and Answers

31.

A network switch adds 100 microseconds of latency and a frame crosses three switches. The switching latency alone is

Answer: C

Correct answer: 300 microseconds

Each switch contributes its own latency, and they accumulate along the path:

\[ 3 \times 100 = 300\ \mathrm{\mu s} \]

The figure is only part of the delay. Transmission time for the frame, propagation along the wiring, and queueing at each output port when other virtual links are contending must be added to it. Bounding the queueing term is the hard part of certifying such a network, and it is what the bandwidth allocation gaps make tractable.

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32.

A single parity bit detects an odd number of bit errors. The probability it misses a two bit error in a word is

Answer: D

Correct answer: 1, it always misses them

Parity works by making the total count of ones odd. Two bit errors change that count by two - either both up, both down, or one each way - and in every case the parity is unchanged, so the word passes the check.

A single parity bit therefore detects every odd number of errors and no even number at all. That is its known limit, and ARINC 429 accepts it because a burst of noise usually corrupts many bits and because the next update of the parameter arrives within milliseconds.

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33.

Replacing 200 individual analogue wires each weighing 15 grams per metre with one twisted pair of 60 grams per metre saves, over 30 metres,

Answer: A

The wires weigh \( 200 \times 15 \times 30 = 90 \) kilograms against \( 60 \times 30 = 1.8 \), a saving of 88.2. Repeated across an airframe this is the weight argument that carried the digital bus. Repeated across a fleet it is decisive.

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34.

A remote terminal must respond to a command within 12 microseconds. At 1 megabit per second this is

Answer: B

Correct answer: 12 bit times

At 1 Mbit/s each bit occupies exactly one microsecond, so the conversion is immediate:

\[ 12\ \mathrm{\mu s} = 12\ \text{bit times} \]

The response time limit exists because MIL-STD-1553 is a scheduled bus: the controller must know when a terminal has failed to answer so that it can move on or retry, and the timeout has to be short enough not to disturb the schedule. Bit times are the natural unit, being independent of any particular clock.

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35.

Statement I: An ARINC 429 reply requires a second bus running the other way.

Statement II: The bus is unidirectional with a single permitted transmitter.

In the light of the above statements, choose the correct answer.

Answer: C

Correct answer: Both Statement I and Statement II are correct

Both are true and the second is the reason for the first. An ARINC 429 bus permits exactly one transmitter and carries data one way only, so a receiver has no means of putting anything on the same wires.

Two-way communication therefore needs two buses, one in each direction. That is the standard's principal cost: a large aircraft accumulates hundreds of such buses, and it is exactly what ARINC 629 and later the switched networks of ARINC 664 were designed to escape.

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36.

Statement I: A receiver that ignores the sign status matrix may act on invalid data.

Statement II: The matrix distinguishes normal operation from failure warning and no computed data.

In the light of the above statements, choose the correct answer.

Answer: D

Both hold and the second is the reason. The transmitter has already declared the word unusable, so the failure lies entirely in the receiving equipment rather than in the bus or the sender. The bus behaved correctly throughout.

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37.

Statement I: MIL-STD-1553 traffic is deterministic.

Statement II: Nothing transmits until the bus controller commands it.

In the light of the above statements, choose the correct answer.

Answer: A

Correct answer: Both Statement I and Statement II are correct

Both are true and the second explains the first. On MIL-STD-1553 no terminal transmits unless the bus controller commands it, so the traffic follows a schedule the controller holds.

Nothing contends for the medium, nothing collides, and the worst-case time to deliver any message can be computed from the schedule. That is what determinism means in this context, and it is why the standard has lasted so long in flight-critical use despite a data rate that has not changed since 1973.

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38.

Statement I: Manchester encoding allows the clock to be recovered from the data.

Statement II: Every bit contains a transition regardless of its value.

In the light of the above statements, choose the correct answer.

Answer: B

Correct answer: Both Statement I and Statement II are correct

Both are true and the second is the mechanism of the first. Manchester encoding puts a transition at the middle of every bit whatever its value, so the receiver sees an edge at a known point in each bit period.

It can therefore lock its own clock to the incoming data, and no separate clock line is needed - which halves the wiring for a serial link. The cost is bandwidth: the signalling rate is twice that of a code without guaranteed transitions.

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39.

Statement I: A single parity bit provides strong error protection.

Statement II: Parity detects any odd number of bit errors in a word.

In the light of the above statements, choose the correct answer.

Answer: C

The second statement is correct but it does not support the first: an even number of errors passes undetected. That blind spot is exactly why later buses use checksums and cyclic redundancy checks. Parity alone is not enough.

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40.

Statement I: Bandwidth allocation gaps make an avionics Ethernet network deterministic.

Statement II: They cap the rate at which any virtual link can inject traffic.

In the light of the above statements, choose the correct answer.

Answer: D

Correct answer: Both Statement I and Statement II are correct

Both are true and the second is how the first is achieved. The bandwidth allocation gap sets a minimum interval between frames on a virtual link, so the link cannot exceed one maximum-size frame per gap.

With every link's traffic bounded in advance and the switches policing those bounds, the total that can arrive at any output port is known, so the worst-case queueing delay can be computed and demonstrated. Ordinary Ethernet offers no such bound, which is why it cannot be certified for flight-critical data as it stands.

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