Logic Gates Questions and Answers

31.

To get an output Y = 1 from the circuit shown, the input A, B and C must be respectively

Logic circuit: inputs A and B go to an OR gate; the OR output and input C go to an AND gate whose output is Y.

A.0, 1, 0
B.1, 0, 0
C.1, 0, 1
D.1, 1, 0

Exam Year(s)

UGC NET - 2012,

Answer: C

The inputs must be A = 1, B = 0 and C = 1, option (C). The circuit passes A and B to an OR gate, and the output of that gate and C go to an AND gate, so \(Y = (A + B)\cdot C\). For Y to be 1, C must be 1 and at least one of A and B must be 1. Option (A), 0, 1, 0, has C = 0, which keeps the AND gate output at 0. Option (B), 1, 0, 0, has C = 0 too. Option (D), 1, 1, 0, also has C = 0. Only option (C) has C = 1 together with a 1 at the OR gate, so it gives Y = 1.

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32.

What will be the output of the following logic diagram ?

Logic diagram with inputs x and y. Each input is also inverted. One AND gate takes x and NOT y; a second AND gate takes NOT x and y. The outputs of the two AND gates feed an OR gate, which gives the output.

A.x OR y
B.x AND y
C.x XOR y
D.x XNOR y

Exam Year(s)

UGC NET - 2013,

Answer: C

The circuit gives x XOR y. The top AND gate receives x and the complement of y, and the bottom AND gate receives the complement of x and y. The OR gate combines them:

\[ F = x \cdot \bar{y} + \bar{x} \cdot y \]

This expression is the exclusive-OR, which is 1 only when x and y differ. OR and AND would not need the inverters, and XNOR is the complement, 1 when the inputs are equal.

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33.

NAND Gate can also be represented by

1. AND - invert Gate
2. OR - Invert Gate
3. Bubbled OR
4. Bubbled AND Which of the following is correct ?

A.1, 2 and 3
B.1 & 2
C.2 & 4
D.1 & 3

Exam Year(s)

UGC NET - 2013,

Answer: D

Statements 1 and 3 are correct, which is option (D). A NAND gate is an AND gate followed by an inverter (AND-invert). By De Morgan's theorem, \(\overline{AB} = \bar{A} + \bar{B}\), so it is equally an OR gate with inverted inputs, which is a bubbled OR. An OR-invert gate is a NOR gate, and a bubbled AND is also a NOR, since \(\bar{A}\bar{B} = \overline{A+B}\). That excludes statements 2 and 4, and with them the options (A), (B) and (C).

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34.

Tri state Buffers provide

(i) reduction of current consumption in the circuit.
(ii) isolation from input to output.
(iii) high impedance during OFF state.
(iv) low impedance during ON state.

A.(i) and (iv)
B.(ii) and (iv)
C.(i) and (ii)
D.(i) and (iii)

Exam Year(s)

UGC NET - 2013,

Answer: D

The key accepts (i) and (iii), the fourth option. A tri-state buffer provides a high impedance state when it is off, which disconnects the output from the line so that many devices can share a bus, and the key also counts the reduction of current drawn from the shared line as a benefit.

The remaining options each carry one of (ii) or (iv), which the key does not accept, so they do not match the key's choice of the fourth option.

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Direction for [ Question No: 35 To 35 ] :

Directions : Q. Nos. 61 to 70, the following items consist of two statements, one labelled the "Assertion (A)" and the other labelled the "Reason (R)". You are to examine these two statements carefully and decide if the Assertion (A) and the Reason (R) are individually true and if so, whether the Reason (R) is a correct explanation of the Assertion (A). Select your answers to these items using the codes given below and mark your answer accordingly.

35.

Assertion (A) : A NAND gate is called a Universal logic element.

Reason (R) : Any logic function can be realized using NAND gates alone.

A.Both (A) and (R) are correct and (R) is correct explanation of (A).
B.Both (A) and (R) are correct, but (R) is not correct explanation of (A).
C.(A) is true, but (R) is false.
D.(A) is false, but (R) is true.

Exam Year(s)

UGC NET - 2013,

Answer: A

Both statements are correct and the reason explains the assertion, the first option. A NAND gate is called universal because any logic function can be realised with NAND gates alone, since NOT, AND and OR can each be built from NANDs.

The reason states exactly this property, so it is the explanation of the assertion. The options calling one of the statements false, or denying the explanation, are wrong.

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36.

Which logic function has the output low only when both inputs are high ?

A.NOR
B.OR
C.AND
D.NAND

Exam Year(s)

UGC NET - 2013,

Answer: D

The logic function whose output is low only when both inputs are high is NAND.

A NAND gate is an AND gate followed by an inverter, so it gives 0 only for the input 1 1 and gives 1 for all the other three input combinations.

AND gives high only when both inputs are high, OR gives low only when both inputs are low, and NOR gives high only when both inputs are low.

Its truth table is 00 gives 1, 01 gives 1, 10 gives 1 and 11 gives 0. A NAND is also a universal gate, since any other gate can be built from NAND gates alone, which is why it is so common in integrated circuits.

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37.

Which one of the following set of gates is best suited for 'parity' checking and 'parity' generation ?

A.AND, OR, NOT
B.NAND, NOR
C.EX-OR, EX-NOR
D.None of the above

Exam Year(s)

UGC NET - 2013,

Answer: C

The EX-OR and EX-NOR gates are best suited for parity checking and generation. The output of an EX-OR gate is 1 when the number of 1 inputs is odd, so a chain of EX-OR gates gives the parity bit of a word, and an EX-NOR gives the complementary parity.

AND, OR and NOT gates, or NAND and NOR gates, can build any function but need many more gates to do the same parity job. Option C is correct. The parity of a word is obtained by taking the EX-OR of all its bits, so a tree of such gates is used both to generate a parity bit and to check it.

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38.

What type of logic circuit is represented by the figure shown below ?

Logic circuit with inputs A and B. Each input goes through a NOT gate and the two inverted signals feed one AND gate. A and B also feed a second AND gate directly. The outputs of the two AND gates feed an OR gate whose output is X.

A.XOR
B.XNOR
C.XAND
D.XNAND

Exam Year(s)

UGC NET - 2013,

Answer: B

The circuit is an XNOR gate. The first AND gate receives the inverted inputs, so it gives the value \(\bar{A}\bar{B}\), and the second AND gate gives AB. The OR gate joins them.

\[ X = \bar{A}\bar{B} + AB \]

This is 1 when the two inputs are equal, which is the truth table of XNOR. An XOR gate gives 1 when the inputs differ, and XAND and XNAND are not standard gates. Option B is correct.

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39.

NAND gate is also called as

A.Bubbled AND gate
B.Bubbled OR gate
C.Bubbled NOR gate
D.Bubbled XOR gate

Exam Year(s)

UGC NET - 2013,

Answer: B

A NAND gate is also called a bubbled OR gate, option (B). By De Morgan's theorem \(\overline{AB} = \bar{A} + \bar{B}\), so a NAND gate behaves as an OR gate with inverted (bubbled) inputs.

A bubbled AND gate (option A) would give \(\bar{A}\bar{B}\), which is the NOR function. A bubbled NOR gate (option C) gives \(\overline{\bar{A}+\bar{B}} = AB\), the AND function, and a bubbled XOR gate (option D) is not a NAND at all.

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40.

Match the following lists :

List - I	List - II
a. IC 7410	i. Hex Inverter
b. IC 7404	ii. Quad 2 input OR gate
c. IC 7432	iii. JK master slave flip flop
d. IC 7472	iv. Triple 3-input NAND gate

A.iv ii i iii
B.iv i ii iii
C.i ii iii iv
D.ii iv i iii

Exam Year(s)

UGC NET - 2013,

Answer: B

The correct match is IC 7410 with the triple 3-input NAND gate (iv), IC 7404 with the hex inverter (i), IC 7432 with the quad 2-input OR gate (ii) and IC 7472 with the JK master-slave flip-flop (iii), so the code is iv i ii iii, option (B).

Options A, C and D exchange some of these, for example giving the hex inverter to the 7410 or the OR gate to the 7404, which does not agree with the data sheets.

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Logic Gates Questions and Answers

Direction for [ Question No: 35 To 35 ] :

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