Shift Registers Questions and Answers

Q: Assertion (A) : Universal shift register can be used to implement accumulator.Reason (R) : Addition and subtraction can be realised using shift registers.

The key takes both statements as true but the Reason as not the explanation of the Assertion.The Assertion is sound: a universal shift register can shift left or right, load in parallel and hold, and a register that loads, holds and shifts is exactly the storage an accumulator needs; shifting also doubles or halves its contents. The Reason is true in a looser sense: serial adders and subtractors are built from shift registers feeding a single full adder with a carry flip-flop.But the accumulator is a register that holds the running result of an arithmetic unit; it is the adder or ALU, not the shifting, that does the addition, so the Reason does not explain why the register can serve as an accumulator. That is why option A is not the key. Neither statement is false, so C and D are out.I could not find a text that discusses this exact pair, so this rests on the key and on the reasoning above, which is the usual reading of such items.

Q: The type of register, in which we have access only to leftmost and rightmost feedback :

The key gives (B) Serial in serial out register.In a serial-in serial-out shift register, data enter at one end, the leftmost stage, and move one stage at each clock pulse until they leave at the other end, the rightmost stage. The stages in between are not accessible from outside, so the only points of access are the two ends. That is the register the question describes.A parallel-in serial-out register lets every stage be loaded in parallel, and a serial-in parallel-out register lets every stage be read, so access is not confined to the ends. The shift left and shift right register is a bidirectional one, defined by the direction of shifting, not by restricted access. The wording of the question is loose, and this is the key's reading.

Q: Consider a 8-bit serial input-parallel output shift registrar operated at clock frequency of 10 MHz. The time taken by the registrar to shift 8 bit number is ..........

The time taken is 800 ns.A serial-in shift register accepts one bit per clock pulse, so loading an 8-bit number takes 8 clock periods. At 10 MHz each period is\[ \begin{aligned} T &= \frac{1}{10 \times 10^{6}\ \text{Hz}} = 100\ \text{ns} \\ t &= 8 \times 100\ \text{ns} = 800\ \text{ns} \end{aligned} \]100 ns is a single clock period, enough for only one bit. 10 µs and 100 ms are far longer than 8 periods of 100 ns and do not follow from the clock frequency.

The given diagram expresses ______.

Four D flip-flops in a row sharing one clock, with a separate input line into each D and a separate output line from each Q

A.Parallel-In Parallel-Out Shift Register
B.Serial-In Parallel-Out Shift Register
C.Serial-In Serial-Out Shift Register
D.Parallel-In Serial-Out Shift Register

Exam Year(s)

DSSSB TGT - 2023,

Answer: A

The diagram shows a parallel-in parallel-out shift register. It has four D flip-flops driven by one common clock, and each flip-flop has its own separate input line into D and its own separate output line from Q. All the bits are loaded together on a clock pulse and are available at the same time at the outputs. In a serial-in register only the first flip-flop would have an external input and the others would take their inputs from the flip-flop before, and in a serial-out register only the last output would be used, which is not what the figure shows.

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Assertion (A) : Universal shift register can be used to implement accumulator.
Reason (R) : Addition and subtraction can be realised using shift registers.

A.Both (A) and (R) are true and (R) is the correct explanation of (A).
B.Both (A) and (R) are true but (R) is not the correct explanation of (A).
C.(A) is true but (R) is false.
D.(A) is false and (R) is true.

Exam Year(s)

MH SET - 2019, SET Exam - 2019,

Answer: B

The key takes both statements as true but the Reason as not the explanation of the Assertion.

The Assertion is sound: a universal shift register can shift left or right, load in parallel and hold, and a register that loads, holds and shifts is exactly the storage an accumulator needs; shifting also doubles or halves its contents. The Reason is true in a looser sense: serial adders and subtractors are built from shift registers feeding a single full adder with a carry flip-flop.

But the accumulator is a register that holds the running result of an arithmetic unit; it is the adder or ALU, not the shifting, that does the addition, so the Reason does not explain why the register can serve as an accumulator. That is why option A is not the key. Neither statement is false, so C and D are out.

I could not find a text that discusses this exact pair, so this rests on the key and on the reasoning above, which is the usual reading of such items.

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The type of register, in which we have access only to leftmost and rightmost feedback :

A.Parallel in serial out register
B.Serial in serial out register
C.Shift left and shift right register
D.Serial in parallel out register

Exam Year(s)

MH SET - 2025, SET Exam - 2025,

Answer: B

The key gives (B) Serial in serial out register.

In a serial-in serial-out shift register, data enter at one end, the leftmost stage, and move one stage at each clock pulse until they leave at the other end, the rightmost stage. The stages in between are not accessible from outside, so the only points of access are the two ends. That is the register the question describes.

A parallel-in serial-out register lets every stage be loaded in parallel, and a serial-in parallel-out register lets every stage be read, so access is not confined to the ends. The shift left and shift right register is a bidirectional one, defined by the direction of shifting, not by restricted access. The wording of the question is loose, and this is the key's reading.

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Consider a 8-bit serial input-parallel output shift registrar operated at clock frequency of 10 MHz. The time taken by the registrar to shift 8 bit number is ..........

A.800 ns
B.100 ms
C.100 ns
D.10 µs

Exam Year(s)

MH SET - 2025, SET Exam - 2025,

Answer: A

The time taken is 800 ns.

A serial-in shift register accepts one bit per clock pulse, so loading an 8-bit number takes 8 clock periods. At 10 MHz each period is

\[ \begin{aligned} T &= \frac{1}{10 \times 10^{6}\ \text{Hz}} = 100\ \text{ns} \\ t &= 8 \times 100\ \text{ns} = 800\ \text{ns} \end{aligned} \]

100 ns is a single clock period, enough for only one bit. 10 µs and 100 ms are far longer than 8 periods of 100 ns and do not follow from the clock frequency.

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Number of flip-flops needed to construct a shift register capable of storing decimal numbers upto 32 are

Exam Year(s)

UGC NET - 2012,

Answer: A

Six flip-flops are needed, option (A). To store a decimal number up to 32 in binary, we have to be able to hold the value 32, which is 100000 and needs six bits. A shift register stores one bit per flip-flop, so six flip-flops are required. Five flip-flops, option (C), can hold the values from 0 to 31 only, because \(2^{5} = 32\) gives 32 combinations. Four, option (B), can hold up to 15, and two, option (D), only up to 3. The reading that the number 32 itself must be stored is what makes the answer six.

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