Logic Gates Questions and Answers

Q: For a NAND gate having two inputs the output is low (0) only :

The output of a two-input NAND gate is low only when both inputs are high.NAND is AND followed by NOT: \(Y = \overline{A \cdot B}\). The AND of the inputs is 1 only when A = 1 and B = 1, so the NAND output is 0 only in that one case and 1 for the other three input combinations.ABY001011101110Both inputs low, or one high and one low, all give a high output, so the other options describe cases where the output is 1.

Q: An OR gate in positive logic functions as :

A positive-logic OR gate functions as an AND gate in negative logic.In positive logic, high = 1 and low = 0, and an OR gate gives a high output whenever any input is high, so its output is low only when all inputs are low. In negative logic the meanings flip: low = 1 and high = 0. Read that way, the same gate gives an output of 1 (low) only when all inputs are 1 (low), which is the AND function.This is De Morgan's duality in hardware: \(\overline{A + B} = \overline{A}\cdot\overline{B}\). The gate does not invert, so it cannot become NAND, NOR or NOT by a change of logic convention alone.

Q: How many entries will be there in the truth table of a 3 input NAND gate ?

The truth table has 8 entries.Each input can be 0 or 1, so n inputs give 2n combinations. For three inputs, 23 = 8 rows, from 000 to 111. For a NAND gate the output is 0 only in the row 111 and 1 in the other seven.3 counts the inputs rather than the combinations, 6 is 2 × 3, and 9 is 32, none of which is the number of binary input combinations.

Q: Using Boolean equation, the output 'Y' of the network shown below is equal to :

The output is \( Y = X_{0}X_{1}X_{3}\ldots X_{n-1} + X_{2}X_{3}X_{5}\ldots X_{n-1} \) \( + \ldots + X_{n-2}X_{n-1} + X_{n} \).The gates alternate AND and OR. Work along the chain:\[ \begin{aligned} G_{1} &= X_{0}X_{1} \\ G_{2} &= X_{0}X_{1} + X_{2} \\ G_{3} &= X_{0}X_{1}X_{3} + X_{2}X_{3} \end{aligned} \]Each AND gate multiplies every existing term by its new input, and each OR gate adds its input as a new term. Every term therefore carries all the AND-gate inputs after it (\( X_{3}, X_{5}, \ldots, X_{n-1} \)), and the final OR adds \( X_{n} \) alone.All-OR, \( X_{0} + X_{1} + \ldots + X_{n} \), would need every gate to be an OR. The sum of pairs ignores the cascading, and the first option multiplies in inputs such as \( X_{2} \) and \( X_{n} \) that enter through OR gates.

Q: The output of the following logic circuit is :In the circuit, inputs A and B feed an OR gate; the OR output and input C feed a NAND gate; inputs D and E feed an AND gate whose output passes through a NOT gate; the outputs of the first NAND gate and the NOT gate feed a final NAND gate, whose output is the output of the circuit.

The output is (A + B)C + DE.Trace the gates. The OR gate gives A + B. The first NAND gate gives X = NOT((A + B)C). The AND gate and inverter give Y = NOT(DE). The final NAND gate gives:\[ \begin{aligned} \overline{X \cdot Y} &= \overline{X} + \overline{Y} \\ &= (A + B)C + DE \end{aligned} \]by De Morgan's theorem, since each inverted term is inverted back. The option (A + B)C + D + E forgets that D and E pass through an AND gate, and the other options mix up the OR and AND stages.

Q: For even number of 1's at the input or inputs having all 0's, the output of EX-NOR gate is :

The output of an EX-NOR gate is High.EX-NOR is the complement of EX-OR. An EX-OR gate gives 1 when an odd number of its inputs are 1 (it is an odd-parity detector), so the EX-NOR gives 1 when the number of 1s is even, including the case of all inputs 0 (zero 1s, which is even).For two inputs: 00 gives 1, 01 and 10 give 0, 11 gives 1. So the output is not Low, and it is perfectly defined.

Q: The most suitable gates to check whether the number of ones in a digital word is even or odd is :

The most suitable gates are EX-OR gates.The output of an exclusive-OR is 1 when an odd number of its inputs are 1. Chaining EX-OR gates across all the bits of a word (\(b_{0} \oplus b_{1} \oplus \dots \oplus b_{n}\)) therefore gives 1 if the number of ones is odd and 0 if it is even. This is how parity generators and parity checkers are built, for example in the 74180 and 74280 chips.NAND and NOR are universal gates, so a parity circuit could in principle be built from them, but only by first making EX-OR functions from several gates each. AND and OR alone cannot detect parity, since they cannot tell two ones from one.

Q: Identify the function 'F' generated by the logic network shown below :

The function is F = ABC.Write the output of each gate:\[ \begin{aligned} \text{OR gate} &: A + \bar{B} \\ \text{lower AND} &: BC \\ F &= (A + \bar{B})BC \end{aligned} \]Expanding,\[ F = ABC + \bar{B}BC = ABC + 0 = ABC \]since \(B\bar{B} = 0\). The first option forgets the inverter on B and uses an OR in the wrong place, the second treats the final AND gate as an OR, and BC(B + A) simplifies to BC, which is true even when A is 0, unlike the network.

Q: The following digital circuit acts as a :

The circuit is a half-subtractor.Reading the gates:\[ \begin{aligned} X_{out} &= A\bar{B} + \bar{A}B = A \oplus B \\ Y_{out} &= \bar{A}B \end{aligned} \]For the subtraction A - B of two bits, the difference is \(A \oplus B\) and a borrow is needed only when A = 0 and B = 1, which is \(\bar{A}B\). So \(X_{out}\) is the difference and \(Y_{out}\) the borrow.A half-adder has the same XOR output but its second output, the carry, is AB, not \(\bar{A}B\). Nothing in the circuit switches between adding and subtracting, so it is neither a half-adder/subtractor nor a 2's complement adder/subtractor.

Q: Given Logic Gate represents which of the following Truth Table ?

The gate gives the truth table A = 0, Q = 1; A = 1, Q = 0.A NOR gate outputs 1 only when all its inputs are 0. With both inputs tied to A, the output is \(\overline{A + A} = \overline{A}\), so the gate acts as an inverter: A = 0 gives Q = 1, and A = 1 gives Q = 0.Option A is a constant 0, option B a constant 1, and option C is a buffer (Q = A), none of which a NOR gate with tied inputs produces.

11.

For a NAND gate having two inputs the output is low (0) only :

A.When both inputs are high
B.When both inputs are low
C.When any one of the inputs is high and other is low
D.When a specified input is high and other is low

Exam Year(s)

MH SET - 2018, SET Exam - 2018,

Answer: A

The output of a two-input NAND gate is low only when both inputs are high.

NAND is AND followed by NOT: \(Y = \overline{A \cdot B}\). The AND of the inputs is 1 only when A = 1 and B = 1, so the NAND output is 0 only in that one case and 1 for the other three input combinations.

A	B	Y
0	0	1
0	1	1
1	0	1
1	1	0

Both inputs low, or one high and one low, all give a high output, so the other options describe cases where the output is 1.

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12.

An OR gate in positive logic functions as :

A.AND gate in Negative logic
B.NAND gate in Negative logic
C.NOR gate in Negative logic
D.NOT gate in Negative logic

Exam Year(s)

MH SET - 2018, SET Exam - 2018,

Answer: A

A positive-logic OR gate functions as an AND gate in negative logic.

In positive logic, high = 1 and low = 0, and an OR gate gives a high output whenever any input is high, so its output is low only when all inputs are low. In negative logic the meanings flip: low = 1 and high = 0. Read that way, the same gate gives an output of 1 (low) only when all inputs are 1 (low), which is the AND function.

This is De Morgan's duality in hardware: \(\overline{A + B} = \overline{A}\cdot\overline{B}\). The gate does not invert, so it cannot become NAND, NOR or NOT by a change of logic convention alone.

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13.

How many entries will be there in the truth table of a 3 input NAND gate ?

Exam Year(s)

MH SET - 2018, SET Exam - 2018,

Answer: D

The truth table has 8 entries.

Each input can be 0 or 1, so n inputs give 2ⁿ combinations. For three inputs, 2³ = 8 rows, from 000 to 111. For a NAND gate the output is 0 only in the row 111 and 1 in the other seven.

3 counts the inputs rather than the combinations, 6 is 2 × 3, and 9 is 3², none of which is the number of binary input combinations.

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14.

Using Boolean equation, the output 'Y' of the network shown below is equal to :

A chain of gates numbered 1 to n: gate 1 is an AND of X0 and X1, gate 2 an OR with X2, gate 3 an AND with X3, and so on, gate n-1 an AND with Xn-1, and gate n an OR with Xn giving Y

A.\( X_{0}X_{1}X_{2}\ldots X_{n} + X_{1}X_{2}.......X_{n} \) \( + X_{2}X_{3}.......X_{n} + X_{n} \)
B.\( X_{0}X_{1} + X_{2}X_{3} + ....... + X_{n-1}X_{n} \)
C.\( X_{0} + X_{1} + X_{2} + ....... + X_{n} \)
D.\( X_{0}X_{1}X_{3}.......X_{n-1} + X_{2}X_{3}X_{5} \) \( .......X_{n-1} + X_{n-2}X_{n-1} + X_{n} \)

Exam Year(s)

MH SET - 2018, SET Exam - 2018,

Answer: D

The output is \( Y = X_{0}X_{1}X_{3}\ldots X_{n-1} + X_{2}X_{3}X_{5}\ldots X_{n-1} \) \( + \ldots + X_{n-2}X_{n-1} + X_{n} \).

The gates alternate AND and OR. Work along the chain:

\[ \begin{aligned} G_{1} &= X_{0}X_{1} \\ G_{2} &= X_{0}X_{1} + X_{2} \\ G_{3} &= X_{0}X_{1}X_{3} + X_{2}X_{3} \end{aligned} \]

Each AND gate multiplies every existing term by its new input, and each OR gate adds its input as a new term. Every term therefore carries all the AND-gate inputs after it (\( X_{3}, X_{5}, \ldots, X_{n-1} \)), and the final OR adds \( X_{n} \) alone.

All-OR, \( X_{0} + X_{1} + \ldots + X_{n} \), would need every gate to be an OR. The sum of pairs ignores the cascading, and the first option multiplies in inputs such as \( X_{2} \) and \( X_{n} \) that enter through OR gates.

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15.

The output of the following logic circuit is :

In the circuit, inputs A and B feed an OR gate; the OR output and input C feed a NAND gate; inputs D and E feed an AND gate whose output passes through a NOT gate; the outputs of the first NAND gate and the NOT gate feed a final NAND gate, whose output is the output of the circuit.

A.AB + C(D + E)
B.(A + B)C + DE
C.(A + B)C + D + E
D.(AB + C).DE

Exam Year(s)

MH SET - 2019, SET Exam - 2019,

Answer: B

The output is (A + B)C + DE.

Trace the gates. The OR gate gives A + B. The first NAND gate gives X = NOT((A + B)C). The AND gate and inverter give Y = NOT(DE). The final NAND gate gives:

\[ \begin{aligned} \overline{X \cdot Y} &= \overline{X} + \overline{Y} \\ &= (A + B)C + DE \end{aligned} \]

by De Morgan's theorem, since each inverted term is inverted back. The option (A + B)C + D + E forgets that D and E pass through an AND gate, and the other options mix up the OR and AND stages.

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16.

For even number of 1's at the input or inputs having all 0's, the output of EX-NOR gate is :

A.Not defined
B.High
C.Low
D.None of the above

Exam Year(s)

MH SET - 2020, SET Exam - 2020,

Answer: B

The output of an EX-NOR gate is High.

EX-NOR is the complement of EX-OR. An EX-OR gate gives 1 when an odd number of its inputs are 1 (it is an odd-parity detector), so the EX-NOR gives 1 when the number of 1s is even, including the case of all inputs 0 (zero 1s, which is even).

For two inputs: 00 gives 1, 01 and 10 give 0, 11 gives 1. So the output is not Low, and it is perfectly defined.

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17.

The most suitable gates to check whether the number of ones in a digital word is even or odd is :

A.EX-OR
B.NAND
C.NOR
D.AND and OR

Exam Year(s)

MH SET - 2020, SET Exam - 2020,

Answer: A

The most suitable gates are EX-OR gates.

The output of an exclusive-OR is 1 when an odd number of its inputs are 1. Chaining EX-OR gates across all the bits of a word (\(b_{0} \oplus b_{1} \oplus \dots \oplus b_{n}\)) therefore gives 1 if the number of ones is odd and 0 if it is even. This is how parity generators and parity checkers are built, for example in the 74180 and 74280 chips.

NAND and NOR are universal gates, so a parity circuit could in principle be built from them, but only by first making EX-OR functions from several gates each. AND and OR alone cannot detect parity, since they cannot tell two ones from one.

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18.

Identify the function 'F' generated by the logic network shown below :

A and the inverse of B feed an OR gate; B and C feed an AND gate; the outputs of these two gates feed a second AND gate whose output is F

A.F = (A + B) C
B.\(F = C + B + \bar{B}A\)
C.F = BC (B + A)
D.F = ABC

Exam Year(s)

MH SET - 2023, SET Exam - 2023,

Answer: D

The function is F = ABC.

Write the output of each gate:

\[ \begin{aligned} \text{OR gate} &: A + \bar{B} \\ \text{lower AND} &: BC \\ F &= (A + \bar{B})BC \end{aligned} \]

Expanding,

\[ F = ABC + \bar{B}BC = ABC + 0 = ABC \]

since \(B\bar{B} = 0\). The first option forgets the inverter on B and uses an OR in the wrong place, the second treats the final AND gate as an OR, and BC(B + A) simplifies to BC, which is true even when A is 0, unlike the network.

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19.

The following digital circuit acts as a :

Inputs A and B each also pass through an inverter; one AND gate takes A and the inverse of B, a second AND gate takes the inverse of A and B, and an OR gate combines these two to give Xout; a third AND gate takes the inverse of A and B to give Yout

A.Half-Subtractor
B.Half-Adder
C.Half-Adder/Subtractor
D.2's complement Adder/ Subtractor

Exam Year(s)

MH SET - 2023, SET Exam - 2023,

Answer: A

The circuit is a half-subtractor.

Reading the gates:

\[ \begin{aligned} X_{out} &= A\bar{B} + \bar{A}B = A \oplus B \\ Y_{out} &= \bar{A}B \end{aligned} \]

For the subtraction A - B of two bits, the difference is \(A \oplus B\) and a borrow is needed only when A = 0 and B = 1, which is \(\bar{A}B\). So \(X_{out}\) is the difference and \(Y_{out}\) the borrow.

A half-adder has the same XOR output but its second output, the carry, is AB, not \(\bar{A}B\). Nothing in the circuit switches between adding and subtracting, so it is neither a half-adder/subtractor nor a 2's complement adder/subtractor.

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20.

Given Logic Gate represents which of the following Truth Table ?

A NOR gate whose two inputs are both connected to the single input A; its output is Q

A.A = 0, Q = 0; A = 1, Q = 0
B.A = 0, Q = 1; A = 1, Q = 1
C.A = 0, Q = 0; A = 1, Q = 1
D.A = 0, Q = 1; A = 1, Q = 0

Exam Year(s)

MH SET - 2024, SET Exam - 2024,

Answer: D

The gate gives the truth table A = 0, Q = 1; A = 1, Q = 0.

A NOR gate outputs 1 only when all its inputs are 0. With both inputs tied to A, the output is \(\overline{A + A} = \overline{A}\), so the gate acts as an inverter: A = 0 gives Q = 1, and A = 1 gives Q = 0.

Option A is a constant 0, option B a constant 1, and option C is a buffer (Q = A), none of which a NOR gate with tied inputs produces.

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