Virtual Memory Organisation Questions and Answers

Q: Which type of memory allows computer system to execute computer programs requiring more memory than physically available ?

The memory is virtual memory.Virtual memory gives each program an address space larger than physical memory. Pages are kept on disk and brought into main memory when referenced, with the page table mapping virtual to physical addresses, so a program can run even if it does not fit in RAM.Auxiliary memory is the disk storage itself, associative memory is content-addressable memory used for lookups such as the TLB, and cache memory speeds up access but does not enlarge the address space.

Q: A CPU generates 32-bit virtual addresses. The page size in 4KB. The processor has a translation look-aside Buffer (TLB) which can hold a total of 128 pages table entries and is 4-way set associative. The maximum size of the TLB tag is :

The maximum TLB tag size is 15 bits.Work out the virtual page number, then the bits used to index the TLB sets:\[ \begin{aligned} \text{offset} &= \log_{2} 4096 = 12 \text{ bits} \\ \text{page number} &= 32 - 12 = 20 \text{ bits} \\ \text{sets} &= 128 / 4 = 32 = 2^{5} \\ \text{tag} &= 20 - 5 = 15 \text{ bits} \end{aligned} \]20 bits would be the tag of a fully associative TLB, where the whole page number is compared. 11 and 13 bits come from subtracting the wrong number of index bits.

Q: What is the purpose of the TLB (Translation Lookaside Buffer) in virtual memory systems ?

The TLB's purpose is to cache page table entries.Translating a virtual address needs the page table, which lives in main memory. Reading it on every access would double the memory traffic. The TLB is a small, fast associative cache that holds recently used page-to-frame translations, so most translations take one quick lookup instead of a page table walk.It does not store program data, which is the job of the data cache. It does not buffer I/O, and interrupt vectors are held in the interrupt vector table, not the TLB.

Which type of memory allows computer system to execute computer programs requiring more memory than physically available ?

A.Auxiliary Memory
B.Associative Memory
C.Cache Memory
D.Virtual Memory

Exam Year(s)

MH SET - 2024, SET Exam - 2024,

Answer: D

The memory is virtual memory.

Virtual memory gives each program an address space larger than physical memory. Pages are kept on disk and brought into main memory when referenced, with the page table mapping virtual to physical addresses, so a program can run even if it does not fit in RAM.

Auxiliary memory is the disk storage itself, associative memory is content-addressable memory used for lookups such as the TLB, and cache memory speeds up access but does not enlarge the address space.

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A CPU generates 32-bit virtual addresses. The page size in 4KB. The processor has a translation look-aside Buffer (TLB) which can hold a total of 128 pages table entries and is 4-way set associative. The maximum size of the TLB tag is :

A.11 bits
B.13 bits
C.15 bits
D.20 bits

Exam Year(s)

MH SET - 2025, SET Exam - 2025,

Answer: C

The maximum TLB tag size is 15 bits.

Work out the virtual page number, then the bits used to index the TLB sets:

\[ \begin{aligned} \text{offset} &= \log_{2} 4096 = 12 \text{ bits} \\ \text{page number} &= 32 - 12 = 20 \text{ bits} \\ \text{sets} &= 128 / 4 = 32 = 2^{5} \\ \text{tag} &= 20 - 5 = 15 \text{ bits} \end{aligned} \]

20 bits would be the tag of a fully associative TLB, where the whole page number is compared. 11 and 13 bits come from subtracting the wrong number of index bits.

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What is the purpose of the TLB (Translation Lookaside Buffer) in virtual memory systems ?

A.Store frequently used data
B.Cache page table entries
C.Buffer I/O operations
D.Store interrupt vectors

Exam Year(s)

Tripura Public Service Commission - 2026,

Answer: B

The TLB's purpose is to cache page table entries.

Translating a virtual address needs the page table, which lives in main memory. Reading it on every access would double the memory traffic. The TLB is a small, fast associative cache that holds recently used page-to-frame translations, so most translations take one quick lookup instead of a page table walk.

It does not store program data, which is the job of the data cache. It does not buffer I/O, and interrupt vectors are held in the interrupt vector table, not the TLB.

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The virtual address generated by a CPU is 32 bits. The Translation Look-aside Buffer (TLB) can hold total 64 page table entries and a 4-way set associative (i.e. with 4 cache lines in the set). The page size is 4 KB. The minimum size of TLB tag is

A.12 bits
B.15 bits
C.16 bits
D.20 bits

Exam Year(s)

UGC NET - 2013,

Answer: C

The minimum TLB tag is 16 bits. A 4 KB page needs 12 bits for the offset, so the page number of a 32-bit virtual address has 20 bits. The TLB has 64 entries in 4-way set associative organisation, which gives 16 sets and needs 4 bits to choose a set.

\[ \text{tag} = 20 - 4 = 16 \]

12 bits is just the offset, 15 bits would suit 32 sets and 20 bits would apply to a fully associative TLB with no index bits, which this one is not.

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Translation Look-aside Buffer (TLB) is

A.a cache-memory in which item to be searched is compared one-by-one with the keys.
B.a cache-memory in which item to be searched is compared with all the keys simultaneously.
C.an associative memory in which item to be searched is compared one-by-one with the keys.
D.an associative memory in which item to be searched is compared with all the keys simultaneously.

Exam Year(s)

UGC NET - 2013,

Answer: D

The Translation Look-aside Buffer is an associative memory in which the item to be searched is compared with all the keys simultaneously. It holds recently used page table entries, and a hardware search of all entries at once gives the frame number quickly.

A one-by-one comparison would be sequential and slow, which defeats the purpose of the TLB. The cache-memory versions are not the established description, which calls the TLB an associative memory.

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