Consider the unsigned 8-bit fixed point binary number representation below,b7 b6 b5 b4 b3 . b2 b1 b0where the position of the binary point is between b3 and b2. Assume b7 is the most significant bit. Some of the decimal numbers listed below cannot be represented exactly in the above representation:(i) 31.500 (ii) 0.875 (iii) 12.100 (iv) 3.001Which one of the following statements is true?

The numbers that cannot be represented exactly are (iii) and (iv) only.The format has five integer bits (b7 to b3), so integer parts from 0 to 31, and three fraction bits (b2 to b0), so fractions in steps of 1/8 = 0.125.31.500 = 11111.100 in binary: representable.0.875 = 7/8 = 00000.111: representable.12.100 needs 0.1, which is not a multiple of 1/8 (in binary it does not terminate): not representable.3.001 needs 0.001, smaller than the step 0.125: not representable.So the claims that (i) or (ii) cannot be represented are false, and so is 'none can be represented'.

Computer Arithmetic Questions and Answers

Q: Consider a carry lookahead adder for adding two \(n\)-bit integers, built using gates of fan-in at most two. The time to perform addition using this adder is

The addition time is \(\Theta(\log(n))\).A carry lookahead adder computes generate and propagate signals for every bit pair, then combines them to find all the carries at once instead of rippling. Each carry \(c_{i}\) is an AND-OR expression over up to \(i\) generate and propagate terms. With gates of fan-in at most two, an AND or OR of \(n\) inputs must be built as a balanced tree of depth \(\log_{2} n\), and the prefix structure of the carry computation also has logarithmic depth. So the delay grows as \(\Theta(\log n)\).\(\Theta(1)\) would need unbounded fan-in. \(\Theta(n)\) is the ripple-carry adder, which carry lookahead is designed to beat, and \(\Theta(\sqrt{n})\) is typical of carry-skip or carry-select designs, not full lookahead.

Q: Consider a system that uses 5 bits for representing signed integers in 2’s complement format. In this system, two integers \(A\) and \(B\) are represented as \(A\)=01010 and \(B\)=11010. Which one of the following operations will result in either an arithmetic overflow or an arithmetic underflow?

The operation that overflows is \(A - B\).Five-bit two's complement represents −16 to +15. A = 01010 = +10, and B = 11010 = 26 − 32 = −6. Then:A + B = 10 − 6 = 4: in rangeA − B = 10 + 6 = 16: above +15, overflowB − A = −6 − 10 = −16: exactly the most negative value, in range2 * B = −12: in rangeSo only A − B leaves the representable range. The trap is B − A: −16 looks extreme but is representable as 10000, because two's complement has one more negative value than positive.

Q: Consider the real valued variables X, Y and Z represented using the IEEE 754 single-precision floating-point format. The binary representations of X and Y in hexadecimal notation are as follows:X: 35C00000 Y: 34A00000Let Z = X + Y.Which one of the following is the binary representation of Z, in hexadecimal notation?

Z is 35E80000.Decode the two operands (sign, 8-bit biased exponent, 23-bit fraction):\[ \begin{aligned} X &= 0\ 01101011\ 1000\ldots \\ &= 1.1_{2} \times 2^{107-127} = 1.5 \times 2^{-20} \\ Y &= 0\ 01101001\ 0100\ldots \\ &= 1.01_{2} \times 2^{105-127} = 1.25 \times 2^{-22} \end{aligned} \]Align Y to X's exponent and add:\[ \begin{aligned} Y &= 0.3125 \times 2^{-20} \\ Z &= 1.8125 \times 2^{-20} = 1.1101_{2} \times 2^{-20} \end{aligned} \]The exponent field stays 107 = 01101011 and the fraction is 1101 followed by zeros, so Z = 0 01101011 1101 000... = 0011 0101 1110 1000 0000... = 35E80000.With the same exponent field, the other options decode to different significands: 35C80000 is \(1.5625 \times 2^{-20}\), 35CC0000 is \(1.59375 \times 2^{-20}\) and 35EC0000 is \(1.84375 \times 2^{-20}\), none equal to the sum.

Q: The format of a single-precision floating-point number as per the IEEE 754 standard is:Sign (1bit)Exponent (8 bits)Mantissa (23 bits)Choose the largest floating-point number among the following options.

The largest number is 0 1111 1110 1111 1111 1111 1111 1111 111.All four have sign bit 0, so they are positive, and a larger exponent field gives a larger number. The exponent 1111 1111 is reserved: with a non-zero mantissa it encodes NaN (not a number), so the third pattern is not a number at all and cannot be the largest.The largest usable exponent is 1111 1110 (254, an actual exponent of 127), and with an all-ones mantissa this pattern is the largest finite single-precision value, about \(3.4 \times 10^{38}\).The first and fourth patterns have exponent 0111 1111 (127, an actual exponent of 0), giving values just under 2 and exactly 1.

Q: Let R1 and R2 be two 4-bit registers that store numbers in 2's complement form. For the operation R1+R2, which one of the following values of R1 and R2 gives an arithmetic overflow?

Overflow occurs for R1 = 1100 and R2 = 1010.In 4-bit two's complement the range is −8 to 7. Overflow happens when two numbers of the same sign give a result outside that range, which shows as a result with the opposite sign.1100 is −4 and 1010 is −6. Their sum is −10, below −8; the 4-bit result is 0110, a positive number, so the addition overflows.The others stay in range: 1011 + 1110 is −5 + (−2) = −7; 0011 + 0100 is 3 + 4 = 7; 1001 + 1111 is −7 + (−1) = −8, the most negative value, still representable.

Q: Consider three floating point numbers \(A\), \(B\) and \(C\) stored in registers RA, RB and RC, respectively as per IEEE-754 single precision floating point format. The 32-bit content stored in these registers (in hexadecimal form) are as follows.RA= 0xC1400000RB = 0x42100000RC = 0x41400000Which one of the following is FALSE?

The false statement is \(C = A + B\).Decode each register as sign, 8-bit exponent with bias 127, and 23-bit fraction with a hidden leading 1.0xC1400000 = 1 10000010 1000...: sign negative, exponent \(130 - 127 = 3\), significand 1.1 in binary = 1.5, so \(A = -1.5 \times 8 = -12\).0x42100000 = 0 10000100 0010...: exponent \(132 - 127 = 5\), significand 1.001 in binary = 1.125, so \(B = 1.125 \times 32 = 36\).0x41400000 = 0 10000010 1000...: exponent 3, significand 1.5, so \(C = 12\).Then \(A + C = -12 + 12 = 0\), \(B = 36 = 3C\) and \(B - C = 24 \gt 0\) are all true, while \(A + B = -12 + 36 = 24\), which is not 12. So \(C = A + B\) is the false statement.

Q: Consider the IEEE-754 single precision floating point numbers P=0xC1800000 and Q=0x3F5C2EF4.Which one of the following corresponds to the product of these numbers (i.e., P × Q), represented in the IEEE-754 single precision format?

The product is 0xC15C2EF4.Decode P: 0xC1800000 is sign 1, exponent 1000 0011 = 131, fraction 0, so \(P = -1.0 \times 2^{131-127} = -16 = -2^{4}\).Multiplying by \(-2^{4}\) flips the sign and adds 4 to the exponent, leaving the significand unchanged. Q = 0x3F5C2EF4 is sign 0, exponent 0111 1110 = 126, and some fraction f. Then:\[ \begin{aligned} \text{sign} &= 1,\quad \text{exponent} = 126 + 4 = 130 \\ 130 &= 1000\,0010_{2} \\ \text{bits} &= 1\ 10000010\ f \end{aligned} \]The leading nine bits 1 1000 0010 followed by the unchanged fraction read as 0xC15C2EF4 (about \(-13.76\), which is \(-16 \times 0.86\)). 0x405C2EF4 and 0x404C2EF4 have a positive sign, and 0xC14C2EF4 alters the fraction bits, which multiplication by a power of two never does.

Consider a carry lookahead adder for adding two \(n\)-bit integers, built using gates of fan-in at most two. The time to perform addition using this adder is

A.\(\Theta(1)\)
B.\(\Theta(\log(n))\)
C.\(\Theta(\sqrt{n})\)
D.\(\Theta(n)\)

Exam Year(s)

GATE CS - 2016,

Answer: B

The addition time is \(\Theta(\log(n))\).

A carry lookahead adder computes generate and propagate signals for every bit pair, then combines them to find all the carries at once instead of rippling. Each carry \(c_{i}\) is an AND-OR expression over up to \(i\) generate and propagate terms. With gates of fan-in at most two, an AND or OR of \(n\) inputs must be built as a balanced tree of depth \(\log_{2} n\), and the prefix structure of the carry computation also has logarithmic depth. So the delay grows as \(\Theta(\log n)\).

\(\Theta(1)\) would need unbounded fan-in. \(\Theta(n)\) is the ripple-carry adder, which carry lookahead is designed to beat, and \(\Theta(\sqrt{n})\) is typical of carry-skip or carry-select designs, not full lookahead.

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Consider a system that uses 5 bits for representing signed integers in 2’s complement format. In this system, two integers \(A\) and \(B\) are represented as \(A\)=01010 and \(B\)=11010. Which one of the following operations will result in either an arithmetic overflow or an arithmetic underflow?

A.\(A + B\)
B.\(A - B\)
C.\(B - A\)
D.\(2 * B\)

Exam Year(s)

GATE CS - 2024,

Answer: B

The operation that overflows is \(A - B\).

Five-bit two's complement represents −16 to +15. A = 01010 = +10, and B = 11010 = 26 − 32 = −6. Then:

A + B = 10 − 6 = 4: in range
A − B = 10 + 6 = 16: above +15, overflow
B − A = −6 − 10 = −16: exactly the most negative value, in range
2 * B = −12: in range

So only A − B leaves the representable range. The trap is B − A: −16 looks extreme but is representable as 10000, because two's complement has one more negative value than positive.

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Consider the real valued variables X, Y and Z represented using the IEEE 754 single-precision floating-point format. The binary representations of X and Y in hexadecimal notation are as follows:

X: 35C00000 Y: 34A00000

Let Z = X + Y.

Which one of the following is the binary representation of Z, in hexadecimal notation?

A.35C80000
B.35CC0000
C.35E80000
D.35EC0000

Exam Year(s)

GATE CS - 2026,

Answer: C

Z is 35E80000.

Decode the two operands (sign, 8-bit biased exponent, 23-bit fraction):

\[ \begin{aligned} X &= 0\ 01101011\ 1000\ldots \\ &= 1.1_{2} \times 2^{107-127} = 1.5 \times 2^{-20} \\ Y &= 0\ 01101001\ 0100\ldots \\ &= 1.01_{2} \times 2^{105-127} = 1.25 \times 2^{-22} \end{aligned} \]

Align Y to X's exponent and add:

\[ \begin{aligned} Y &= 0.3125 \times 2^{-20} \\ Z &= 1.8125 \times 2^{-20} = 1.1101_{2} \times 2^{-20} \end{aligned} \]

The exponent field stays 107 = 01101011 and the fraction is 1101 followed by zeros, so Z = 0 01101011 1101 000... = 0011 0101 1110 1000 0000... = 35E80000.

With the same exponent field, the other options decode to different significands: 35C80000 is \(1.5625 \times 2^{-20}\), 35CC0000 is \(1.59375 \times 2^{-20}\) and 35EC0000 is \(1.84375 \times 2^{-20}\), none equal to the sum.

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The format of a single-precision floating-point number as per the IEEE 754 standard is:

Sign (1bit)

Exponent (8 bits)

Mantissa (23 bits)

Choose the largest floating-point number among the following options.

A.0 0111 1111 1111 1111 1111 1111 1111 111
B.0 1111 1110 1111 1111 1111 1111 1111 111
C.0 1111 1111 1111 1111 1111 1111 1111 111
D.0 0111 1111 0000 0000 0000 0000 0000 000

Exam Year(s)

GATE CS - 2024,

Answer: B

The largest number is 0 1111 1110 1111 1111 1111 1111 1111 111.

All four have sign bit 0, so they are positive, and a larger exponent field gives a larger number. The exponent 1111 1111 is reserved: with a non-zero mantissa it encodes NaN (not a number), so the third pattern is not a number at all and cannot be the largest.

The largest usable exponent is 1111 1110 (254, an actual exponent of 127), and with an all-ones mantissa this pattern is the largest finite single-precision value, about \(3.4 \times 10^{38}\).

The first and fourth patterns have exponent 0111 1111 (127, an actual exponent of 0), giving values just under 2 and exactly 1.

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Consider the unsigned 8-bit fixed point binary number representation below,

b₇ b₆ b₅ b₄ b₃ . b₂ b₁ b₀

where the position of the binary point is between b₃ and b₂. Assume b₇ is the most significant bit. Some of the decimal numbers listed below cannot be represented exactly in the above representation:

(i) 31.500 (ii) 0.875 (iii) 12.100 (iv) 3.001

Which one of the following statements is true?

A.None of (i), (ii), (iii), (iv) can be exactly represented
B.Only (ii) cannot be exactly represented
C.Only (iii) and (iv) cannot be exactly represented
D.Only (i) and (ii) cannot be exactly represented

Exam Year(s)

GATE CS - 2018,

Answer: C

The numbers that cannot be represented exactly are (iii) and (iv) only.

The format has five integer bits (b7 to b3), so integer parts from 0 to 31, and three fraction bits (b2 to b0), so fractions in steps of 1/8 = 0.125.

31.500 = 11111.100 in binary: representable.
0.875 = 7/8 = 00000.111: representable.
12.100 needs 0.1, which is not a multiple of 1/8 (in binary it does not terminate): not representable.
3.001 needs 0.001, smaller than the step 0.125: not representable.

So the claims that (i) or (ii) cannot be represented are false, and so is 'none can be represented'.

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Let R1 and R2 be two 4-bit registers that store numbers in 2's complement form. For the operation R1+R2, which one of the following values of R1 and R2 gives an arithmetic overflow?

A.R1 = 1011 and R2 = 1110
B.R1 = 1100 and R2 = 1010
C.R1 = 0011 and R2 = 0100
D.R1 = 1001 and R2 = 1111

Exam Year(s)

GATE CS - 2022,

Answer: B

Overflow occurs for R1 = 1100 and R2 = 1010.

In 4-bit two's complement the range is −8 to 7. Overflow happens when two numbers of the same sign give a result outside that range, which shows as a result with the opposite sign.

1100 is −4 and 1010 is −6. Their sum is −10, below −8; the 4-bit result is 0110, a positive number, so the addition overflows.

The others stay in range: 1011 + 1110 is −5 + (−2) = −7; 0011 + 0100 is 3 + 4 = 7; 1001 + 1111 is −7 + (−1) = −8, the most negative value, still representable.

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Consider three floating point numbers \(A\), \(B\) and \(C\) stored in registers R_A, R_B and R_C, respectively as per IEEE-754 single precision floating point format. The 32-bit content stored in these registers (in hexadecimal form) are as follows.

R_A= 0xC1400000

R_B = 0x42100000

R_C = 0x41400000

Which one of the following is FALSE?

A.\(A + C = 0\)
B.\(C = A + B\)
C.\(B = 3C\)
D.\((B - C) \gt 0\)

Exam Year(s)

GATE CS - 2022,

Answer: B

The false statement is \(C = A + B\).

Decode each register as sign, 8-bit exponent with bias 127, and 23-bit fraction with a hidden leading 1.

0xC1400000 = 1 10000010 1000...: sign negative, exponent \(130 - 127 = 3\), significand 1.1 in binary = 1.5, so \(A = -1.5 \times 8 = -12\).
0x42100000 = 0 10000100 0010...: exponent \(132 - 127 = 5\), significand 1.001 in binary = 1.125, so \(B = 1.125 \times 32 = 36\).
0x41400000 = 0 10000010 1000...: exponent 3, significand 1.5, so \(C = 12\).

Then \(A + C = -12 + 12 = 0\), \(B = 36 = 3C\) and \(B - C = 24 \gt 0\) are all true, while \(A + B = -12 + 36 = 24\), which is not 12. So \(C = A + B\) is the false statement.

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Consider the IEEE-754 single precision floating point numbers P=0xC1800000 and Q=0x3F5C2EF4.

Which one of the following corresponds to the product of these numbers (i.e., P × Q), represented in the IEEE-754 single precision format?

A.0x404C2EF4
B.0x405C2EF4
C.0xC15C2EF4
D.0xC14C2EF4

Exam Year(s)

GATE CS - 2023,

Answer: C

The product is 0xC15C2EF4.

Decode P: 0xC1800000 is sign 1, exponent 1000 0011 = 131, fraction 0, so \(P = -1.0 \times 2^{131-127} = -16 = -2^{4}\).

Multiplying by \(-2^{4}\) flips the sign and adds 4 to the exponent, leaving the significand unchanged. Q = 0x3F5C2EF4 is sign 0, exponent 0111 1110 = 126, and some fraction f. Then:

\[ \begin{aligned} \text{sign} &= 1,\quad \text{exponent} = 126 + 4 = 130 \\ 130 &= 1000\,0010_{2} \\ \text{bits} &= 1\ 10000010\ f \end{aligned} \]

The leading nine bits 1 1000 0010 followed by the unchanged fraction read as 0xC15C2EF4 (about \(-13.76\), which is \(-16 \times 0.86\)). 0x405C2EF4 and 0x404C2EF4 have a positive sign, and 0xC14C2EF4 alters the fraction bits, which multiplication by a power of two never does.

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