IO Organisation and Interrupts Questions and Answers

Q: Which one of the following statements is FALSE?

The FALSE statement is Programmed I/O has better CPU utilization than interrupt driven I/O.In programmed I/O the CPU repeatedly polls the device status and waits while the device is busy, so it wastes cycles doing nothing useful. Interrupt driven I/O lets the CPU do other work and respond only when the device signals readiness, so it uses the CPU better, not worse.The other statements are true. In cycle stealing the DMA controller takes the bus for one word at a time. Burst mode transfers a whole block while holding the bus, so it has higher throughput for bulk data. With vectored interrupts the device supplies the address of its service routine, so the CPU need not poll to find the source and can start the routine sooner.

Q: Suppose a program is running on a non-pipelined single processor computer system. The computer is connected to an external device that can interrupt the processor asynchronously. The processor needs to execute the interrupt service routine (ISR) to serve this interrupt. The following steps (not necessarily in order) are taken by the processor when the interrupt arrives:(i) The processor saves the content of the program counter.(ii) The program counter is loaded with the start address of the ISR.(iii) The processor finishes the present instruction.Which ONE of the following is the CORRECT sequence of steps?

The correct sequence is (iii), (i), (ii).A non-pipelined processor checks for interrupts only at instruction boundaries, so it first finishes the present instruction (iii); an instruction left half done could not be resumed cleanly. It then saves the program counter (i), which now holds the address of the next instruction, so that execution can return there after the ISR. Only then is the PC loaded with the start address of the ISR (ii), transferring control to the handler.Saving the PC before finishing the instruction (options starting with (i)) would save the wrong return address. Loading the ISR address before saving the PC, as in (iii), (ii), (i), would overwrite the return address and lose it.

Q: Consider a computer with a 4 MHz processor. Its DMA controller can transfer 8 bytes in 1 cycle from a device to main memory through cycle stealing at regular intervals. Which one of the following is the data transfer rate (in bits per second) of the DMA controller if 1% of the processor cycles are used for DMA?

The transfer rate is 25,60,000 bits per second.The processor has \(4 \times 10^{6}\) cycles per second, and 1% of them, 40,000 cycles, go to DMA. Each stolen cycle moves 8 bytes:\[ \begin{aligned} 40000 \times 8 &= 320000\ \text{bytes/s} \\ 320000 \times 8 &= 2560000\ \text{bits/s} \end{aligned} \]That is 2.56 million bits per second, written 25,60,000 in the Indian grouping.2,56,000 is ten times too small, and 3,200 and 32,000 are far smaller still, though 40,000 transfers of 64 bits each happen every second.

Q: Consider the following two statements about interrupt handling mechanisms in a CPU.S1: In non-vectored interrupt mechanism, it usually takes more time to start the Interrupt Service Routine (ISR) when compared to that in a vectored interrupt mechanism.S2: In daisy-chain interrupt mechanism, the CPU polls all the input devices individually to determine the source of the interrupt.Which one of the following options is correct with respect to S1 and S2 ?

S1 is true and S2 is false.S1: In a vectored interrupt scheme, the interrupting device supplies a vector that points the CPU straight at its service routine. In a non-vectored scheme, the CPU jumps to a fixed location and must then find out which device interrupted, usually by polling, before reaching the right ISR. So starting the ISR typically takes longer, and S1 is true.S2: Daisy chaining is a hardware priority scheme. The interrupt-acknowledge signal passes from device to device along the chain, and the first requesting device stops it and places its identifying vector on the bus. The CPU does not poll each device; that describes software polling. So S2 is false.

Q: The following are some events that occur after a device controller issues an interrupt while process \(L\) is under execution.(P) The processor pushes the process status of \(L\) onto the control stack.(Q) The processor finishes the execution of the current instruction.(R) The processor executes the interrupt service routine.(S) The processor pops the process status of \(L\) from the control stack.(T) The processor loads the new PC value based on the interrupt.Which one of the following is the correct order in which the events above occur?

The correct order is QPTRS.(Q) The processor finishes the instruction it is executing; interrupts are checked between instructions.(P) It saves the status of process L on the control stack, so L can be resumed.(T) It loads the PC with the address of the interrupt service routine.(R) It runs the interrupt service routine.(S) It restores L's status from the stack and L continues.PTRSQ saves the status before the current instruction completes, TRPQS jumps to the handler without first saving L's state, and QTPRS loads the new PC before saving the old state, which would lose L's return address.

Q: Which one of the following facilitates transfer of bulk data from hard disk to main memory with the highest throughput?

The highest throughput for bulk transfers comes from DMA based I/O transfer.With direct memory access, the DMA controller moves whole blocks between the disk controller and main memory itself, interrupting the CPU only once when the block is done. The data does not pass through CPU registers, so large transfers run at close to the bus and device rate.In programmed I/O and polling the CPU moves every word and spends its time checking device status. Interrupt-driven I/O frees the CPU from polling, but it still takes an interrupt and moves data per word or small unit, and the interrupt overhead limits throughput for bulk data.

Q: Strobe and Handshaking are mechanisms used to solve problems associated with :

Strobe and handshaking solve the problems of Asynchronous I/O synchronization.When the CPU and an I/O device run on independent clocks, the transfer is asynchronous, and the receiver has no common clock to tell it when valid data is on the bus. Control signals have to coordinate the timing. In the strobe method one unit pulses a strobe line to say when data is valid. In handshaking, a second control line lets the receiver acknowledge that it has taken the data, so each step is confirmed.The problem these mechanisms address is therefore timing coordination, synchronisation, in asynchronous transfer. Synchronous transfer needs neither, because both units share a clock.

Q: One of the following cannot be classified as an Interrupt :

The one that is not a class of interrupt is Memory.Interrupts are described as priority interrupts (serviced according to a priority scheme), daisy-chained interrupts (devices connected in series so that priority follows position in the chain) and non-maskable interrupts (which cannot be disabled by the processor, such as power failure).Memory is a hardware component, not a kind of interrupt, even though a memory error can raise one.

Q: Which of the following task is performed by Direct Memory Access (DMA) in a computer system ?

DMA allows data transfer between a storage unit and main memory independent of the CPU.A DMA controller takes over the system buses (the CPU grants them in response to a bus request) and moves a block of data directly between an I/O device and memory. The CPU only initialises the transfer and is interrupted when it ends, so it is free during the transfer.Transfers under CPU control are programmed or interrupt-driven I/O, which DMA replaces. DMA does not bypass memory to talk to the CPU, and transfers between the CPU and memory are ordinary memory access, not DMA.

Which one of the following statements is FALSE?

A.In the cycle stealing mode of DMA, one word of data is transferred between an I/O device and main memory in a stolen cycle
B.For bulk data transfer, the burst mode of DMA has a higher throughput than the cycle stealing mode
C.Programmed I/O mechanism has a better CPU utilization than the interrupt driven I/O mechanism
D.The CPU can start executing an interrupt service routine faster with vectored interrupts than with non-vectored interrupts

Exam Year(s)

GATE CS - 2024,

Answer: C

The FALSE statement is Programmed I/O has better CPU utilization than interrupt driven I/O.

In programmed I/O the CPU repeatedly polls the device status and waits while the device is busy, so it wastes cycles doing nothing useful. Interrupt driven I/O lets the CPU do other work and respond only when the device signals readiness, so it uses the CPU better, not worse.

The other statements are true. In cycle stealing the DMA controller takes the bus for one word at a time. Burst mode transfers a whole block while holding the bus, so it has higher throughput for bulk data. With vectored interrupts the device supplies the address of its service routine, so the CPU need not poll to find the source and can start the routine sooner.

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Suppose a program is running on a non-pipelined single processor computer system. The computer is connected to an external device that can interrupt the processor asynchronously. The processor needs to execute the interrupt service routine (ISR) to serve this interrupt. The following steps (not necessarily in order) are taken by the processor when the interrupt arrives:

(i) The processor saves the content of the program counter.
(ii) The program counter is loaded with the start address of the ISR.
(iii) The processor finishes the present instruction.

Which ONE of the following is the CORRECT sequence of steps?

A.(iii), (i), (ii)
B.(i), (iii), (ii)
C.(i), (ii), (iii)
D.(iii), (ii), (i)

Exam Year(s)

GATE CS - 2025,

Answer: A

The correct sequence is (iii), (i), (ii).

A non-pipelined processor checks for interrupts only at instruction boundaries, so it first finishes the present instruction (iii); an instruction left half done could not be resumed cleanly. It then saves the program counter (i), which now holds the address of the next instruction, so that execution can return there after the ISR. Only then is the PC loaded with the start address of the ISR (ii), transferring control to the handler.

Saving the PC before finishing the instruction (options starting with (i)) would save the wrong return address. Loading the ISR address before saving the PC, as in (iii), (ii), (i), would overwrite the return address and lose it.

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Consider a computer with a 4 MHz processor. Its DMA controller can transfer 8 bytes in 1 cycle from a device to main memory through cycle stealing at regular intervals. Which one of the following is the data transfer rate (in bits per second) of the DMA controller if 1% of the processor cycles are used for DMA?

A.2,56,000
B.3,200
C.25,60,000
D.32,000

Exam Year(s)

GATE CS - 2024,

Answer: C

The transfer rate is 25,60,000 bits per second.

The processor has \(4 \times 10^{6}\) cycles per second, and 1% of them, 40,000 cycles, go to DMA. Each stolen cycle moves 8 bytes:

\[ \begin{aligned} 40000 \times 8 &= 320000\ \text{bytes/s} \\ 320000 \times 8 &= 2560000\ \text{bits/s} \end{aligned} \]

That is 2.56 million bits per second, written 25,60,000 in the Indian grouping.

2,56,000 is ten times too small, and 3,200 and 32,000 are far smaller still, though 40,000 transfers of 64 bits each happen every second.

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Consider the following two statements about interrupt handling mechanisms in a CPU.

S1: In non-vectored interrupt mechanism, it usually takes more time to start the Interrupt Service Routine (ISR) when compared to that in a vectored interrupt mechanism.
S2: In daisy-chain interrupt mechanism, the CPU polls all the input devices individually to determine the source of the interrupt.

Which one of the following options is correct with respect to S1 and S2 ?

A.Both S1 and S2 are true
B.Both S1 and S2 are false
C.S1 is true and S2 is false
D.S1 is false and S2 is true

Exam Year(s)

GATE CS - 2026,

Answer: C

S1 is true and S2 is false.

S1: In a vectored interrupt scheme, the interrupting device supplies a vector that points the CPU straight at its service routine. In a non-vectored scheme, the CPU jumps to a fixed location and must then find out which device interrupted, usually by polling, before reaching the right ISR. So starting the ISR typically takes longer, and S1 is true.

S2: Daisy chaining is a hardware priority scheme. The interrupt-acknowledge signal passes from device to device along the chain, and the first requesting device stops it and places its identifying vector on the bus. The CPU does not poll each device; that describes software polling. So S2 is false.

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The following are some events that occur after a device controller issues an interrupt while process \(L\) is under execution.

(P) The processor pushes the process status of \(L\) onto the control stack.
(Q) The processor finishes the execution of the current instruction.
(R) The processor executes the interrupt service routine.
(S) The processor pops the process status of \(L\) from the control stack.
(T) The processor loads the new PC value based on the interrupt.

Which one of the following is the correct order in which the events above occur?

A.QPTRS
B.PTRSQ
C.TRPQS
D.QTPRS

Exam Year(s)

GATE CS - 2018,

Answer: A

The correct order is QPTRS.

(Q) The processor finishes the instruction it is executing; interrupts are checked between instructions.
(P) It saves the status of process L on the control stack, so L can be resumed.
(T) It loads the PC with the address of the interrupt service routine.
(R) It runs the interrupt service routine.
(S) It restores L's status from the stack and L continues.

PTRSQ saves the status before the current instruction completes, TRPQS jumps to the handler without first saving L's state, and QTPRS loads the new PC before saving the old state, which would lose L's return address.

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Which one of the following facilitates transfer of bulk data from hard disk to main memory with the highest throughput?

A.DMA based I/O transfer
B.Interrupt driven I/O transfer
C.Polling based I/O transfer
D.Programmed I/O transfer

Exam Year(s)

GATE CS - 2022,

Answer: A

The highest throughput for bulk transfers comes from DMA based I/O transfer.

With direct memory access, the DMA controller moves whole blocks between the disk controller and main memory itself, interrupting the CPU only once when the block is done. The data does not pass through CPU registers, so large transfers run at close to the bus and device rate.

In programmed I/O and polling the CPU moves every word and spends its time checking device status. Interrupt-driven I/O frees the CPU from polling, but it still takes an interrupt and moves data per word or small unit, and the interrupt overhead limits throughput for bulk data.

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Strobe and Handshaking are mechanisms used to solve problems associated with :

A.Synchronous I/O communication
B.Asynchronous I/O communication
C.Synchronous I/O synchronization
D.Asynchronous I/O synchronization

Exam Year(s)

MH SET - 2019, SET Exam - 2019,

Answer: D

Strobe and handshaking solve the problems of Asynchronous I/O synchronization.

When the CPU and an I/O device run on independent clocks, the transfer is asynchronous, and the receiver has no common clock to tell it when valid data is on the bus. Control signals have to coordinate the timing. In the strobe method one unit pulses a strobe line to say when data is valid. In handshaking, a second control line lets the receiver acknowledge that it has taken the data, so each step is confirmed.

The problem these mechanisms address is therefore timing coordination, synchronisation, in asynchronous transfer. Synchronous transfer needs neither, because both units share a clock.

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One of the following cannot be classified as an Interrupt :

A.Priority
B.Daisy chaining
C.Non-maskable
D.Memory

Exam Year(s)

MH SET - 2020, SET Exam - 2020,

Answer: D

The one that is not a class of interrupt is Memory.

Interrupts are described as priority interrupts (serviced according to a priority scheme), daisy-chained interrupts (devices connected in series so that priority follows position in the chain) and non-maskable interrupts (which cannot be disabled by the processor, such as power failure).

Memory is a hardware component, not a kind of interrupt, even though a memory error can raise one.

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Which of the following task is performed by Direct Memory Access (DMA) in a computer system ?

A.allow data transfer between a storage unit and CPU independent of memory
B.allow data transfer between a storage unit and main memory independent of CPU
C.allow data transfer between a storage unit and main memory under CPU control
D.allow data transfer between CPU and main memory independent of a storage unit

Exam Year(s)

MH SET - 2024, SET Exam - 2024,

Answer: B

DMA allows data transfer between a storage unit and main memory independent of the CPU.

A DMA controller takes over the system buses (the CPU grants them in response to a bus request) and moves a block of data directly between an I/O device and memory. The CPU only initialises the transfer and is interrupted when it ends, so it is free during the transfer.

Transfers under CPU control are programmed or interrupt-driven I/O, which DMA replaces. DMA does not bypass memory to talk to the CPU, and transfers between the CPU and memory are ordinary memory access, not DMA.

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10.

Which of the following generally does not use a Software Interrupt ?

A.Software Timer
B.System Timer
C.Page Fault
D.Task Switching

Exam Year(s)

MH SET - 2025, SET Exam - 2025,

Answer: B

The one that generally does not use a software interrupt is the system timer.

The system timer is a hardware device that raises a hardware interrupt at fixed intervals. The operating system uses these ticks for timekeeping and scheduling, but the interrupt itself comes from the hardware.

The others are generated within the processor or by software. A page fault is an exception, an internal interrupt raised while an instruction runs. Task switching is invoked through system calls and software-generated interrupts or traps, and software timers are maintained by the kernel and serviced through software interrupts.

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