Communication Protocols in Embedded Systems Questions and Answers

Answer: A

The receiver recovers timing from the start bit and then samples at intervals it derives from its own clock, which is why the two ends must agree on the baud rate in advance. A synchronous link such as SPI carries the clock alongside the data.

Answer: B

Eight data bits, no parity and one stop bit is the ordinary configuration, and with the start bit it makes ten bit times per character. Both ends must agree on all of it, since a mismatch shows up as a framing error rather than as an obvious failure.

Answer: C

Correct answer: 10

8N1 means eight data bits, no parity and one stop bit, and every asynchronous character is also preceded by a start bit: \[ 1 + 8 + 0 + 1 = 10. \] That ten is the number to hold, because it makes every throughput calculation on such a link a simple division of the baud rate by ten.

Answer: D

Correct answer: the stop bit was not found where it was expected

The receiver samples where the stop bit should be and expects to find the line idle. Finding it low instead means the framing assumption has broken - almost always a baud rate mismatch, so that the receiver’s bit clock has drifted out of alignment across the character, but sometimes noise or a break condition. A parity error and an overrun are separate flags reporting separate faults.

Answer: A

Correct answer: 960 characters per second

With ten bit times per character, \[ \frac{9600}{10} = 960\ \mathrm{characters/s}. \] Baud is bits per second on the wire, and the start and stop bits are on the wire, so twenty per cent of the link’s capacity carries framing rather than data. The 1067 offered divides by nine and forgets one of them.

Answer: B

Correct answer: 250 ms

\[ \frac{240\ \mathrm{characters}}{960\ \mathrm{characters/s}} = 0.25\ \mathrm{s} = 250\ \mathrm{ms}, \] or equivalently \( 240\times10 = 2400 \) bits at 9600 bits per second. A quarter of a second to send a 240-character line is worth remembering, because it is long enough that a system polling such a link inside a control loop will miss deadlines unless the transfer is handled by interrupt or DMA.

Answer: C

The receiver resynchronises only on the start bit, so a two per cent error has grown to twenty per cent of a bit time by the tenth, which is close to the sampling margin. Roughly two per cent combined is the usual working limit.

Answer: D

Correct answer: four wires: clock, two data lines and a select

SPI uses a clock, a master-out line, a master-in line and a slave select - four wires to the first device. The two separate data lines make it full duplex, and because the clock is supplied by the master there is no baud rate to agree and no framing to lose, which is why SPI runs comfortably at tens of megahertz where a UART does not.

Answer: A

Mode zero has an idle-low clock with data sampled on the rising edge; the four modes are the combinations of the two bits. A slave sampling on the wrong edge returns plausible but wrong data, which is a common first-bring-up fault.

Answer: B

Shifting a byte out of the master shifts one in from the slave on the same clocks, so a read is performed by sending a dummy byte. Devices that have nothing to send return a fixed pattern, which is worth knowing when debugging.