Logic Gates Questions and Answers

Answer: C

Correct answer: Parallel adder

In a ripple carry chain each stage must wait for the carry from the one below it, so the delay accumulates. The question's intended contrast is with a parallel adder, in which the bits are presented and added simultaneously rather than passed along a serial chain.

Answer: D

Correct answer: OR gate

In negative logic the roles of the two voltage levels are exchanged, and by De Morgan's law that turns AND into OR: \( (A'\cdot B')' = A + B \). So a gate that is AND for positive logic is OR for negative logic.

Answer: B

Correct answer: False

AND gives 1 when all inputs are HIGH, so its output in that case is HIGH, not LOW. It is NAND that goes LOW there.

Answer: D

Correct answer: NAND

By De Morgan's law \( \overline{A}+\overline{B} = \overline{A\cdot B} \), which is the NAND function. It is the expression for a NAND written with the inversion pushed inwards onto the variables.

Answer: C

Correct answer: the two inputs are unequal

XOR gives 1 when its inputs differ and 0 when they agree, so equal inputs - both 0 or both 1 - produce a LOW output.

Answer: A

Correct answer: OR

NOR is NOT-OR, so it is an OR gate with its output inverted.

Answer: C

In OR gate  we need atleast one bit to be equal to 1 to generate the output as 1 because OR means  any of the condition out of two is equal to 1  which means  if atleast one input is 1 then it shows output as 1 . Number of 1's in input may be more than one but the output will always be 1 in OR gate. So the answer is 'C'.

Answer: B

Correct answer: to select 1 out of N input data sources and to transmit it to a single channel

A multiplexer is a data selector: the control lines choose one of its inputs and connect it to the single output. The reverse operation - one input to one of many outputs - is the demultiplexer.

Answer: D

Correct answer: A = 0, B = 0, C = 0

NOR is the complement of OR, and OR is 0 only when every input is 0. So the NOR output is HIGH in that single case out of eight.

Answer: A

Correct answer: competitive with TTL

Early CMOS was markedly slower than TTL, but successive process improvements have brought its switching speed to roughly the same level, which is why CMOS has taken over while keeping its advantage in power.