Match List I with List II and select the correct answer using codes given below the list :List IList II(a) S1 = 0, S0 = 0(i) OPCODE FETCH(b) S1 = 0, S0 = 1(ii) READ(c) S1 = 1, S0 = 0(iii) HALT(d) S1 = 1, S0 = 1(iv) WRITE

The correct matching is a-iii, b-iv, c-ii, d-i.The 8085 status signals S1 and S0 identify the type of machine cycle:S1 = 0, S0 = 0: HALT (iii)S1 = 0, S0 = 1: memory or I/O WRITE (iv)S1 = 1, S0 = 0: memory or I/O READ (ii)S1 = 1, S0 = 1: OPCODE FETCH (i)Opcode fetch has both bits set, which rules out the code pairing it with 00, and the code that pairs 01 with READ swaps the read and write cycles.

Microprocessors and Microcontrollers Questions and Answers

Q: What is the order decided by a processor or the CPU of a controller to execute an instruction ?

The order is fetch, decode, execute.A processor first fetches the instruction from memory at the address held in the program counter, then decodes it to determine the operation and operands, and only then executes it. The cycle then repeats for the next instruction.An instruction cannot be decoded before it has been fetched, nor executed before it has been decoded, so every other ordering among the options is impossible.

What is the order decided by a processor or the CPU of a controller to execute an instruction ?

A.Decode, fetch, execute
B.Execute, fetch, decode
C.Fetch, execute, decode
D.Fetch, decode, execute

Exam Year(s)

MH SET - 2018, SET Exam - 2018,

Answer: D

The order is fetch, decode, execute.

A processor first fetches the instruction from memory at the address held in the program counter, then decodes it to determine the operation and operands, and only then executes it. The cycle then repeats for the next instruction.

An instruction cannot be decoded before it has been fetched, nor executed before it has been decoded, so every other ordering among the options is impossible.

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Match List I with List II and select the correct answer using codes given below the list :

List I	List II
(a) S1 = 0, S0 = 0	(i) OPCODE FETCH
(b) S1 = 0, S0 = 1	(ii) READ
(c) S1 = 1, S0 = 0	(iii) HALT
(d) S1 = 1, S0 = 1	(iv) WRITE

A.a-i, b-ii, c-iii, d-iv
B.a-iii, b-iv, c-ii, d-i
C.a-ii, b-i, c-iv, d-iii
D.a-iv, b-i, c-ii, d-iii

Exam Year(s)

MH SET - 2018, SET Exam - 2018,

Answer: B

The correct matching is a-iii, b-iv, c-ii, d-i.

The 8085 status signals S1 and S0 identify the type of machine cycle:

S1 = 0, S0 = 0: HALT (iii)
S1 = 0, S0 = 1: memory or I/O WRITE (iv)
S1 = 1, S0 = 0: memory or I/O READ (ii)
S1 = 1, S0 = 1: OPCODE FETCH (i)

Opcode fetch has both bits set, which rules out the code pairing it with 00, and the code that pairs 01 with READ swaps the read and write cycles.

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