Interrupts and DMA Questions and Answers

Answer: B

RST 6 transfers execution to 0030 H.

The 8085 restart instruction RST n is a one-byte call to the address 8 × n. For n = 6 that is 48 in decimal, which is 30 in hexadecimal, so the vector is 0030H.

0024H is the vector of the TRAP interrupt (RST 4.5). 0048H writes the decimal value 48 as if it were hexadecimal, and 0060H would correspond to n = 12, which does not exist among RST 0 to RST 7.

Answer: C

SIM stands for set interrupt mask.

SIM takes the contents of the accumulator and uses them to mask or unmask the RST 7.5, 6.5 and 5.5 interrupts, reset the RST 7.5 flip-flop, and send a bit on the serial output data line SOD. Its companion RIM (read interrupt mask) reads the mask status, pending interrupts and the serial input SID.

'Select', 'sort' and 'subscribe' do not appear in the 8085 mnemonics; they are distractors built on the same initials.

Answer: D

The fastest I/O data transfer uses DMA.

In direct memory access, a DMA controller takes over the system bus and moves data directly between the I/O device and memory, without the processor fetching and executing an instruction for each byte. Transfers run at bus speed, which is why disks and other high-speed devices use DMA for block transfers.

Polled I/O wastes processor time testing device status, and interrupt-driven I/O still needs the processor to run a service routine for every transfer. Memory-mapped I/O is a way of addressing I/O ports, not a transfer method, and its transfers still pass through the processor.

Answer: C

These terms are used in direct memory access.

In DMA, a DMA controller must take over the system bus from the processor to transfer data directly between memory and a peripheral. It requests the bus (Bus Request, or HOLD in the 8085/8086), the processor grants it (Bus Grant, HLDA), and the logic that decides which master gets the bus is bus arbitration.

Serial communication, memory map design and address/data multiplexing involve no transfer of bus mastership, so these terms do not belong to them.

Answer: B

From lowest to highest priority the order is (1) (2) (3) (4): single step, INTR, NMI, divide error/INT n/INTO.

In the 8086 the internal (software and exception) interrupts such as divide error, INT n and INTO have the highest priority, followed by the non-maskable interrupt NMI, then the maskable hardware interrupt INTR. The single-step (trap) interrupt has the lowest priority.

Option A makes single step the highest priority, the reverse of the truth, and options C and D place NMI below INTR, so none matches the 8086 priority list.