Computer Network Questions and Answers

Answer: C

The toolkit for building grids is the Globus toolkit.

The Globus Toolkit is open-source software for grid computing. It provides the services needed to share computing power and data across institutions: security, resource management, data transfer (GridFTP) and information services.

Apache Hadoop is a framework for distributed storage and processing of big data on clusters. Microsoft Azure is a commercial cloud computing platform. Microsoft Word is a word processor. None of them is a grid-building toolkit.

Answer: B

Correct answer: True

The statement is true. The NOT gate, or inverter, has a single input and produces its complement: 0 becomes 1 and 1 becomes 0. Its Boolean expression is \( Y = \bar{A} \). It is the only basic gate with one input; every other takes two or more. On a diagram it is drawn as a triangle with a small circle at the output, and that circle - the bubble - is the general symbol for inversion, which is why NAND is drawn as AND with a bubble and NOR as OR with one. Two inverters in series cancel, giving \( \bar{\bar{A}} = A \), which is the involution law of Boolean algebra. Pairs of inverters are nevertheless used deliberately as buffers, to restore signal strength without changing the logic. An inverter is easily made from either universal gate by tying the inputs together: a NAND or a NOR with both inputs joined behaves exactly as a NOT.

Answer: B

Correct answer: baseband signal

The signal as it comes from the source, before it is modulated onto a carrier, is the baseband signal. The carrier is what it is later imposed on.

Answer: C

Correct answer: both inputs are HIGH

A NAND gate is an AND gate followed by an inverter, so its output is the complement of AND. AND gives 1 only when both inputs are 1; NAND therefore gives 0 only in that single case and 1 in the other three. Its truth table is worth holding in mind: 0,0 gives 1; 0,1 gives 1; 1,0 gives 1; 1,1 gives 0. NAND is called a universal gate because every other logic function can be built from it alone. An inverter is a NAND with both inputs tied together; an AND is a NAND followed by another NAND acting as an inverter; an OR is a NAND fed by two inverting NANDs, which is De Morgan’s theorem in hardware. NOR is universal for the same reason. That property matters in practice, since a manufacturer can build an entire logic family from one repeated cell.

Answer: A

Correct answer: is faster than main memory and holds recently used data

Cache is a small, very fast memory placed between the processor and main memory, holding copies of data and instructions that have recently been used or are likely to be used next. It works because of the principle of locality. Temporal locality means a location just accessed is likely to be accessed again soon; spatial locality means nearby locations are likely to be accessed next, which is why data is fetched in whole cache lines rather than single bytes. A request found in cache is a hit and is served in a few processor cycles; a miss requires main memory and costs hundreds. Because hit rates in practice exceed 90 per cent, the average access time approaches that of the cache. It is built from SRAM, which uses a flip-flop per bit and needs no refreshing, unlike the DRAM of main memory - faster but far more expensive per bit, which is why cache is small. Modern processors use several levels, L1 through L3.

Answer: B

Correct answer: the time between an input change and the corresponding output change

Propagation delay is the time taken for a change at the input to appear at the output. It is measured between the 50 per cent points of the two transitions, and it is usually quoted separately for a low-to-high and a high-to-low transition, since the two are rarely equal. It is the fundamental limit on clock speed. The longest chain of gates between two flip-flops - the critical path - must settle within one clock period, so the maximum frequency is the reciprocal of that total delay plus the flip-flop’s own setup time. It is also why a ripple counter is slower than a synchronous one: each stage waits for the one below it, and the delays accumulate. The fourth option describes fan-out, the number of gate inputs a single output can drive, which is a different specification and is itself limited by current and by the loading capacitance that increases the delay.

Answer: C

Correct answer: Registers and cache

Registers sit inside the processor itself, and cache - at least its first level - is fabricated on the same die, so both are reached without a transaction on the external memory bus. That proximity is what makes them fast. The memory hierarchy arranges storage by the trade-off between speed, capacity and cost per bit. Registers are fastest and smallest; L1, L2 and L3 cache follow; then main memory in DRAM; then solid-state and magnetic disk; then optical media and tape at the bottom, slowest and cheapest. Everything below cache is reached over a bus and takes hundreds or millions of cycles rather than one. Only the top three levels are directly addressable by instructions at all. Disk, optical media and tape are secondary storage: their contents must be copied into main memory before the processor can operate on them, which is what an operating system’s input and output subsystem exists to arrange.

Answer: A

Correct answer: Its output can be logic 0, logic 1, or a high-impedance state

A tri-state buffer has an ordinary data input, an output, and an enable control. When enabled it passes the input through; when disabled its output enters a high-impedance state, effectively disconnecting it from the wire. That third state is not a logic level. It is the electrical condition of being neither driving high nor driving low, and it is what makes shared buses possible. Many devices can be wired to the same set of conductors provided that only one is enabled at a time; the rest float and do not interfere. Without it, two outputs driving the same line at opposite levels would create a short circuit from supply to ground - called bus contention - which wastes power and can damage the devices. The high-impedance state is written Z in truth tables and simulation. The alternative arrangement for a shared line is the open-collector or open-drain output with a pull-up resistor.

Answer: A

Correct answer: Physical

A bridge works at the data link layer, so the addresses it reads and learns are the physical, or MAC, addresses in the frame header. Network addresses are inside the payload, where a bridge does not look.

Answer: B

Correct answer: half-duplex

A single track carries trains in both directions but only one at a time, which is exactly half duplex. A double track would be full duplex.