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Embedded System Architecture Questions and Answers

51.

An 8-bit register has bits 2:0 selecting a prescaler of two raised to that field. Writing 0x05 selects a prescaler of

Answer: C

Correct answer: 32

The field holds 5, and the prescaler is two raised to that field: \[ 2^5 = 32. \] Reading the register value as the divisor directly gives the 5 offered, and this is a common form for prescaler fields precisely because a three-bit field then spans divisors from 1 to 128.

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Answer: D

The boundary is one of degree rather than kind: a phone's SoC carries several processor clusters, a graphics unit, radio basebands and video codecs. Both classes integrate memory and peripherals and both need external supplies and passives.

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Answer: A

The mask set for an ASIC costs millions and cannot be altered, so it pays only at volume; an FPGA carries a much higher unit cost and power but can be reconfigured in the field. The crossover volume is the whole of the decision.

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Answer: B

A single-cycle multiply-accumulate, circular addressing for delay lines and bit-reversed addressing for transforms are the characteristic features. Modern general purpose cores have absorbed much of this in their vector units, which has narrowed the gap considerably.

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Answer: C

True concurrency is what fabric gives and a single core cannot: a hundred independent counters run at once in an FPGA and are time-shared on a processor. Cost, power and ease of programming all favour the microcontroller.

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Answer: D

Between about a volt and the guaranteed operating minimum a device may execute instructions wrongly and corrupt its own flash, so the detector asserts reset through that band. A separate oscillator start-up timer handles the crystal.

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Answer: A

Releasing reset before the supply is valid or the clock is running gives unpredictable start-up, so the delay covers both. Most devices now integrate the whole arrangement, which is why an external RC network is no longer usual.

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Answer: B

Halting the core, reading registers and memory, setting breakpoints and writing flash are all done over the same few pins. It was designed for boundary-scan board testing, and debug access was added to the same interface later.

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59.

Match the block with its function.

1. Watchdog timer   2. DMA controller   3. Interrupt vector table

P. Holds the handler addresses   Q. Resets a hung system   R. Moves data without the core

Answer: C

Correct answer: 1-Q, 2-R, 3-P

Three independent blocks. The watchdog must be refreshed periodically by working software and resets the device if it is not, so it recovers a hung system. The DMA controller transfers data between memory and peripherals without the core, freeing it for other work. The interrupt vector table holds the addresses of the handlers, which the core reads when an interrupt is taken.

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60.

Match the memory with its property.

1. SRAM   2. Flash   3. Mask ROM

P. Written once at manufacture   Q. Volatile and fast   R. Non-volatile and block-erasable

Answer: D

The three cover the three cases a design has to choose between: working store, updatable program store, and the cheapest possible program store at very high volume. Mask ROM survives only where volumes are enormous and the code will never change.

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