Combinational CMOS Logic Design Questions and Answers

Q: In CMOS logic circuits the p-MOS transistor acts as :

The p-MOS transistors act as the pull-up network.A CMOS gate has a pull-up network of p-MOS transistors between VDD and the output and a complementary pull-down network of n-MOS transistors between the output and ground. A p-MOS transistor conducts when its gate is low and passes a strong logic 1, so it is used to pull the output up to VDD; the n-MOS network passes a strong 0 and pulls it down.The pull-down role belongs to the n-MOS transistors. In a properly designed CMOS gate neither network is a short to ground or a passive load; the p-MOS 'load' belongs to older pseudo-nMOS logic.

Q: The circuit diagram shown in figure represents :

The circuit is a two input CMOS NOR gate.The output X is pulled up to VDD only through two p-MOS transistors in series, so it goes high only when both are on, that is, when A and B are both 0. The two n-MOS transistors in parallel pull X down to VSS whenever either A or B is 1. The output is therefore 1 only for A = B = 0:\[ X = \overline{A + B} \]A NAND gate has the opposite arrangement, p-MOS in parallel and n-MOS in series. AND and OR gates need an extra inverter stage after the NAND or NOR, which this single-stage circuit does not have.

In CMOS logic circuits the p-MOS transistor acts as :

A.Pull-down network
B.Pull-up network
C.Short to ground
D.Load

Exam Year(s)

MH SET - 2019, SET Exam - 2019,

Answer: B

The p-MOS transistors act as the pull-up network.

A CMOS gate has a pull-up network of p-MOS transistors between V_DD and the output and a complementary pull-down network of n-MOS transistors between the output and ground. A p-MOS transistor conducts when its gate is low and passes a strong logic 1, so it is used to pull the output up to V_DD; the n-MOS network passes a strong 0 and pulls it down.

The pull-down role belongs to the n-MOS transistors. In a properly designed CMOS gate neither network is a short to ground or a passive load; the p-MOS 'load' belongs to older pseudo-nMOS logic.

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The circuit diagram shown in figure represents :

Two p-MOS transistors in series from VDD to the output X and two n-MOS transistors in parallel from X to VSS; input A drives the gates of one p-MOS and one n-MOS and input B drives the gates of the other pair

A.Two input CMOS AND gate
B.Two input CMOS NAND gate
C.Two input CMOS NOR gate
D.Two input CMOS OR gate

Exam Year(s)

MH SET - 2019, SET Exam - 2019,

Answer: C

The circuit is a two input CMOS NOR gate.

The output X is pulled up to V_DD only through two p-MOS transistors in series, so it goes high only when both are on, that is, when A and B are both 0. The two n-MOS transistors in parallel pull X down to V_SS whenever either A or B is 1. The output is therefore 1 only for A = B = 0:

\[ X = \overline{A + B} \]

A NAND gate has the opposite arrangement, p-MOS in parallel and n-MOS in series. AND and OR gates need an extra inverter stage after the NAND or NOR, which this single-stage circuit does not have.

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Combinational CMOS Logic Design Questions and Answers

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