Match the List-I with List II and select the correct answer using the codes given below :List IList II(a) Sequential logic circuits(i) Independent of clock signal(b) Combination logic circuits(ii) Depends on clock signal(c) Synchronous sequential logic(iii) Combinational circuit with storage element as feedback path(d) Asynchronous logic circuits(iv) Decoder, multiplexers

The correct matching is a-iii, b-iv, c-ii, d-i.A sequential logic circuit is a combinational circuit with storage elements in a feedback path, so its output depends on past inputs (iii).Combinational circuits include decoders and multiplexers, whose outputs depend only on present inputs (iv).Synchronous sequential logic changes state only at clock edges, so it depends on the clock signal (ii).Asynchronous logic circuits change state whenever inputs change, independent of a clock (i).The codes that give 'depends on clock signal' to sequential circuits in general, or 'independent of clock' to synchronous logic, confuse the general class with its clocked and unclocked subtypes.

Sequential Circuit Design Questions and Answers

Q: Assertion (A) : In order to synchronise a Mealy type circuits the inputs of the sequential circuit must be synchronized with the clock and the outputs must be sampled only during the clock edge.Reason (R) : In Mealy model the outputs may change if input changes during the clock period and output may have momentary false values.

The answer is both (A) and (R) are true and (R) is the correct explanation of (A).In a Mealy machine the outputs depend on the present state and the present inputs. If an input changes in the middle of a clock period, the output can change at once and may pass through momentary false values (glitches) before settling, which is what R says.That is precisely why A is required: to get clean synchronous behaviour, the inputs are synchronised with the clock and the outputs are read only at the clock edge, when they are guaranteed to be valid. A Moore machine avoids the problem because its outputs depend on the state alone.

Q: Which one of the following options corresponds to the expressions for the inputs of the D flip-flops, D1 and D0?

The correct expressions are \(D_{1} = \bar{P}Q_{1} + \bar{P}Q_{0} + Q_{1}Q_{0}\) and \(D_{0} = \bar{P}\,\overline{Q_{0}} + \bar{P}Q_{1} + Q_{1}\overline{Q_{0}}\).For a D flip-flop the input equals the next state, so \(D_{1} = Q_{1}^{+}\) and \(D_{0} = Q_{0}^{+}\). Read the minterms from the table, written as P Q1 Q0:\(Q_{1}^{+} = 1\) for 001, 010, 011 and 111. The three terms \(\bar{P}Q_{0}\) (001, 011), \(\bar{P}Q_{1}\) (010, 011) and \(Q_{1}Q_{0}\) (011, 111) cover exactly these.\(Q_{0}^{+} = 1\) for 000, 010, 011 and 110. The terms \(\bar{P}\,\overline{Q_{0}}\) (000, 010), \(\bar{P}Q_{1}\) (010, 011) and \(Q_{1}\overline{Q_{0}}\) (010, 110) cover exactly these.The other options fail on a row: for example any \(D_{1}\) containing \(PQ_{1}\) gives 1 for input 110, where the table's next \(Q_{1}\) is 0, and \(D_{0} = PQ_{0} + \dots\) gives 1 for 101, where the next \(Q_{0}\) is 0.

Q: While designing a sequential circuit, the clock signals are used because of :

Clock signals are used to synchronize events in various parts of a system.In a synchronous sequential circuit every flip-flop changes state only at a clock edge. The clock therefore makes all state changes happen together at known instants, so that signals have time to settle between edges and the circuit behaves predictably despite gate delays.The clock signal does not tell the time of day or measure time since power-on; real-time clocks are separate devices. Nor does it carry serial data, which travels on data lines, although a clock may time when each bit is sampled.

Q: A state equation specifies :

A state equation specifies the next state as a function of present state and inputs.In a sequential circuit, a state equation (also called a transition or characteristic equation) gives the value each flip-flop will take after the next clock pulse in terms of the present state and the inputs, for example \(Q(t+1) = D\) for a D flip-flop or \(Q(t+1) = JQ' + K'Q\) for a JK flip-flop.The clock only determines when the transition happens. Combinational circuits have no state, so a state equation cannot describe their behaviour, and the number of arithmetic operations has nothing to do with it.

Q: The following state diagram represents :[State diagram: two states, 0 and 1. Each state has a self-loop labelled 0. An arrow labelled 1 goes from state 0 to state 1, and another arrow labelled 1 goes from state 1 back to state 0.]

The state diagram represents a serial parity checker.The machine has two states. An input 0 leaves the state unchanged, and an input 1 toggles it, from 0 to 1 or from 1 to 0. After a stream of bits, the state therefore shows whether the number of 1s received so far is even (state 0) or odd (state 1), which is exactly the job of a serial parity checker.A serial adder needs to keep a carry and takes two input bits at a time. A shift register and a counter have more states, and a counter advances on every clock regardless of whether the input is 0 or 1.

Q: Output values of Moore type FSM are determined by its ..............

In a Moore machine the outputs are determined by the current state.A Moore FSM attaches its outputs to the states themselves, so the output depends only on which state the machine is in. The inputs affect the output only indirectly, by deciding the next state at the clock edge. That makes Moore outputs change only after a clock edge and keeps them free of glitches from the inputs.In a Mealy machine, by contrast, outputs depend on both the current state and the present inputs, which is why 'input values' describes Mealy rather than Moore. The clock only times the state changes, and 'output values' would be a circular answer.

Q: In FSM diagram what does circle represent ?

In an FSM diagram, a circle represents a state.In a state diagram of a finite state machine, each circle (node) stands for one state of the machine, labelled with its name or code. Arrows between circles are transitions, labelled with the input conditions that cause them and, in a Mealy machine, the outputs. In a Moore machine the output is written inside the state circle.A change of state is shown by an arrow, not a circle. Output values are written on arrows or inside circles but are not what the circle represents. The initial state is one particular state, usually marked by an arrow from nowhere or a double circle, so 'initial state' is too narrow.

Direction for [ Question No: 1 To 1 ] :

Assertion-Reason type questions : The following items consist of two statements, one labelled as 'Assertion (A)', and the other labelled the 'Reason (R)'. You are to examine these two statements and decide if the Assertion (A) and the Reason (R) are individually true and if so, whether the reason is a correct explanation of the Assertion. Select your answer to these items using the codes given below and mark your answer sheet accordingly.

Codes :
(A) Both (A) and (R) are true and (R) is the correct explanation of (A)
(B) Both (A) and (R) are true but (R) is not the correct explanation of (A)
(C) (A) is true but (R) is false
(D) (A) is false and (R) is true

Assertion (A) : In order to synchronise a Mealy type circuits the inputs of the sequential circuit must be synchronized with the clock and the outputs must be sampled only during the clock edge.

Reason (R) : In Mealy model the outputs may change if input changes during the clock period and output may have momentary false values.

A.Both (A) and (R) are true and (R) is the correct explanation of (A)
B.Both (A) and (R) are true but (R) is not the correct explanation of (A)
C.(A) is true but (R) is false
D.(A) is false and (R) is true

Exam Year(s)

MH SET - 2018, SET Exam - 2018,

Answer: A

The answer is both (A) and (R) are true and (R) is the correct explanation of (A).

In a Mealy machine the outputs depend on the present state and the present inputs. If an input changes in the middle of a clock period, the output can change at once and may pass through momentary false values (glitches) before settling, which is what R says.

That is precisely why A is required: to get clean synchronous behaviour, the inputs are synchronised with the clock and the outputs are read only at the clock edge, when they are guaranteed to be valid. A Moore machine avoids the problem because its outputs depend on the state alone.

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Direction for [ Question No: 2 To 2 ] :

Consider a 2-bit saturating up/down counter that performs the saturating up count when the input P is 0, and the saturating down count when P is 1. The Next State table of the counter is as shown. The counter is built as a synchronous sequential circuit using D flip-flops.

Input	Current State		Next State
P	Q₁	Q₀	Q₁⁺	Q₀⁺
0	0	0	0	1
0	0	1	1	0
0	1	0	1	1
0	1	1	1	1
1	0	0	0	0
1	0	1	0	0
1	1	0	0	1
1	1	1	1	0

Which one of the following options corresponds to the expressions for the inputs of the D flip-flops, D₁ and D₀?

A.\(D_{1} = PQ_{1} + \bar{P}Q_{0} + Q_{1}Q_{0}\); \(D_{0} = PQ_{0} + \bar{P}Q_{1} + Q_{1}\overline{Q_{0}}\)
B.\(D_{1} = \bar{P}Q_{1} + \bar{P}Q_{0} + Q_{1}Q_{0}\); \(D_{0} = \bar{P}\,\overline{Q_{0}} + \bar{P}Q_{1} + Q_{1}\overline{Q_{0}}\)
C.\(D_{1} = \bar{P}\,\overline{Q_{1}} + \bar{P}Q_{0} + Q_{1}Q_{0}\); \(D_{0} = \bar{P}Q_{0} + \bar{P}Q_{1} + Q_{1}\overline{Q_{0}}\)
D.\(D_{1} = P\overline{Q_{1}} + \bar{P}Q_{0} + Q_{1}Q_{0}\); \(D_{0} = P\overline{Q_{0}} + \bar{P}Q_{1} + Q_{1}\overline{Q_{0}}\)

Exam Year(s)

GATE CS - 2026,

Answer: B

The correct expressions are \(D_{1} = \bar{P}Q_{1} + \bar{P}Q_{0} + Q_{1}Q_{0}\) and \(D_{0} = \bar{P}\,\overline{Q_{0}} + \bar{P}Q_{1} + Q_{1}\overline{Q_{0}}\).

For a D flip-flop the input equals the next state, so \(D_{1} = Q_{1}^{+}\) and \(D_{0} = Q_{0}^{+}\). Read the minterms from the table, written as P Q₁ Q₀:

\(Q_{1}^{+} = 1\) for 001, 010, 011 and 111. The three terms \(\bar{P}Q_{0}\) (001, 011), \(\bar{P}Q_{1}\) (010, 011) and \(Q_{1}Q_{0}\) (011, 111) cover exactly these.
\(Q_{0}^{+} = 1\) for 000, 010, 011 and 110. The terms \(\bar{P}\,\overline{Q_{0}}\) (000, 010), \(\bar{P}Q_{1}\) (010, 011) and \(Q_{1}\overline{Q_{0}}\) (010, 110) cover exactly these.

The other options fail on a row: for example any \(D_{1}\) containing \(PQ_{1}\) gives 1 for input 110, where the table's next \(Q_{1}\) is 0, and \(D_{0} = PQ_{0} + \dots\) gives 1 for 101, where the next \(Q_{0}\) is 0.

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Which of the given options best describes the truthfulness of the following statements? i) The clock signal is required for sequential circuits. ii) In the sequential circuit, memory elements play an important role and are required.

A.i-True, ii-True
B.i-False, ii-True
C.i-True, ii-False
D.i-False, ii-False

Exam Year(s)

DSSSB TGT - 2023,

Answer: A

Both statements are true. A sequential circuit changes state with a clock signal that times the changes, and its memory elements, such as flip-flops, store the state and are essential, since the output depends on past inputs as well as present ones. So the first option, i-True and ii-True, is correct and the other options each mark at least one true statement as false. Examples of memory elements in such circuits are latches and flip-flops, and examples of sequential circuits are counters and registers.

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Designing of an asynchronous sequential circuits are difficult because of :

A.Memory required is enormous
B.External clock is to be provided
C.They involve stability problem
D.It is more complex

Exam Year(s)

MH SET - 2018, SET Exam - 2018,

Answer: C

Asynchronous sequential circuits are difficult to design because they involve stability problem.

An asynchronous circuit has no clock: its state changes whenever an input changes, and feedback paths with unequal delays decide the next state. Two state variables changing together can race, the circuit can settle in the wrong state or oscillate between states, and hazards can produce false pulses. The designer must ensure the circuit always reaches a stable state, which requires race-free state assignment and careful analysis.

Needing an external clock is the mark of a synchronous circuit, not an asynchronous one. Memory is not the difficulty, and 'more complex' is vague; the stability problem is the specific reason.

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While designing a sequential circuit, the clock signals are used because of :

A.To display the time of the day
B.To carry serial data signals
C.To synchronize events in various parts of a system
D.To display the how much time is elapsed after the system is turned on

Exam Year(s)

MH SET - 2018, SET Exam - 2018,

Answer: C

Clock signals are used to synchronize events in various parts of a system.

In a synchronous sequential circuit every flip-flop changes state only at a clock edge. The clock therefore makes all state changes happen together at known instants, so that signals have time to settle between edges and the circuit behaves predictably despite gate delays.

The clock signal does not tell the time of day or measure time since power-on; real-time clocks are separate devices. Nor does it carry serial data, which travels on data lines, although a clock may time when each bit is sampled.

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Match the List-I with List II and select the correct answer using the codes given below :

List I	List II
(a) Sequential logic circuits	(i) Independent of clock signal
(b) Combination logic circuits	(ii) Depends on clock signal
(c) Synchronous sequential logic	(iii) Combinational circuit with storage element as feedback path
(d) Asynchronous logic circuits	(iv) Decoder, multiplexers

A.a-ii, b-iii, c-i, d-iv
B.a-iii, b-iv, c-ii, d-i
C.a-i, b-iv, c-iii, d-ii
D.a-ii, b-i, c-iv, d-iii

Exam Year(s)

MH SET - 2018, SET Exam - 2018,

Answer: B

The correct matching is a-iii, b-iv, c-ii, d-i.

A sequential logic circuit is a combinational circuit with storage elements in a feedback path, so its output depends on past inputs (iii).
Combinational circuits include decoders and multiplexers, whose outputs depend only on present inputs (iv).
Synchronous sequential logic changes state only at clock edges, so it depends on the clock signal (ii).
Asynchronous logic circuits change state whenever inputs change, independent of a clock (i).

The codes that give 'depends on clock signal' to sequential circuits in general, or 'independent of clock' to synchronous logic, confuse the general class with its clocked and unclocked subtypes.

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A state equation specifies :

A.Next state as a function of present state and inputs
B.Clock applied
C.Behaviour of a combinational circuit
D.Number of arithmetic operations

Exam Year(s)

MH SET - 2019, SET Exam - 2019,

Answer: A

A state equation specifies the next state as a function of present state and inputs.

In a sequential circuit, a state equation (also called a transition or characteristic equation) gives the value each flip-flop will take after the next clock pulse in terms of the present state and the inputs, for example \(Q(t+1) = D\) for a D flip-flop or \(Q(t+1) = JQ' + K'Q\) for a JK flip-flop.

The clock only determines when the transition happens. Combinational circuits have no state, so a state equation cannot describe their behaviour, and the number of arithmetic operations has nothing to do with it.

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The following state diagram represents :

[State diagram: two states, 0 and 1. Each state has a self-loop labelled 0. An arrow labelled 1 goes from state 0 to state 1, and another arrow labelled 1 goes from state 1 back to state 0.]

A.Serial Adder
B.Shift Register
C.Serial Parity Checker
D.Counter

Exam Year(s)

MH SET - 2023, SET Exam - 2023,

Answer: C

The state diagram represents a serial parity checker.

The machine has two states. An input 0 leaves the state unchanged, and an input 1 toggles it, from 0 to 1 or from 1 to 0. After a stream of bits, the state therefore shows whether the number of 1s received so far is even (state 0) or odd (state 1), which is exactly the job of a serial parity checker.

A serial adder needs to keep a carry and takes two input bits at a time. A shift register and a counter have more states, and a counter advances on every clock regardless of whether the input is 0 or 1.

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Output values of Moore type FSM are determined by its ..............

A.Clock input
B.Current state
C.Input values
D.Output values

Exam Year(s)

MH SET - 2024, SET Exam - 2024,

Answer: B

In a Moore machine the outputs are determined by the current state.

A Moore FSM attaches its outputs to the states themselves, so the output depends only on which state the machine is in. The inputs affect the output only indirectly, by deciding the next state at the clock edge. That makes Moore outputs change only after a clock edge and keeps them free of glitches from the inputs.

In a Mealy machine, by contrast, outputs depend on both the current state and the present inputs, which is why 'input values' describes Mealy rather than Moore. The clock only times the state changes, and 'output values' would be a circular answer.

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10.

In FSM diagram what does circle represent ?

A.State
B.Change of state
C.Output value
D.Initial state

Exam Year(s)

MH SET - 2025, SET Exam - 2025,

Answer: A

In an FSM diagram, a circle represents a state.

In a state diagram of a finite state machine, each circle (node) stands for one state of the machine, labelled with its name or code. Arrows between circles are transitions, labelled with the input conditions that cause them and, in a Mealy machine, the outputs. In a Moore machine the output is written inside the state circle.

A change of state is shown by an arrow, not a circle. Output values are written on arrows or inside circles but are not what the circle represents. The initial state is one particular state, usually marked by an arrow from nowhere or a double circle, so 'initial state' is too narrow.

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Sequential Circuit Design Questions and Answers

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