Field Effect Transistors Questions and Answers

Answer: D

The device is the FET.

In a field-effect transistor the current flows through a channel, a thin layer of semiconductor, and the voltage on the gate sets up an electric field across (transverse to) that channel. The field changes the number of carriers in the channel, and so its conductivity, which is how the gate controls the drain current. The name 'field effect' comes from this mechanism.

A BJT is controlled by the injection of carriers across forward-biased junctions, with base current, not by a transverse field. A P-N diode and a Zener diode are two-terminal devices with no control electrode at all.

Answer: D

I_GSS is the gate current when the gate-source junction is reverse-biased.

In a JFET the gate-channel p-n junction is always operated in reverse bias. I_GSS, the gate reverse current or gate leakage current, is the small current that flows into the gate with the drain shorted to the source and a specified reverse voltage applied between gate and source. It is typically in nanoamperes, which is why a JFET has a very high input resistance.

The drain current is I_D (with I_DSS its value at V_GS = 0). The gate-source voltage is V_GS. Forward-biasing the gate junction is avoided in normal operation and is not what I_GSS specifies.

Answer: D

The advantage is better thermal stability.

In a FET, current is carried by majority carriers only, and their mobility falls as temperature rises, so the drain current tends to decrease with heating. This negative temperature coefficient prevents thermal runaway, which can destroy a bipolar transistor. FETs also offer very high input resistance, low noise and small size.

A low input resistance is the opposite of the FET's main advantage, which is its very high input resistance, especially in MOSFETs. 'Big size, small life' is false, since FETs are compact and reliable. High output resistance is not usually listed as the FET's advantage over the BJT.

Answer: D

The operating point is \(V_{DS} = 15\) V, \(I_{D} = 5\) mA.

The divider sets the gate voltage, and the source voltage is taken to sit at about the gate voltage (that is, \(V_{GS} \approx 0\), the approximation the options are built on):

\[ \begin{aligned} V_{G} &= 30 \times \frac{1\ \text{M}\Omega}{3\ \text{M}\Omega} = 10\ \text{V} \\ I_{D} &\approx \frac{V_{G}}{R_{s}} = \frac{10\ \text{V}}{2\ \text{k}\Omega} = 5\ \text{mA} \\ V_{DS} &= 30 - 5\ \text{mA}(1 + 2)\ \text{k}\Omega = 15\ \text{V} \end{aligned} \]

The other options put \(V_{DS}\) in millivolts. With 5 mA the two resistors drop only 15 V, which leaves 15 V, not 15 mV, across the transistor. Currents of 15 mA or 10 mA through the 3 kΩ of \(R_{D}\) and \(R_{s}\) would need 45 V or 30 V, more than or all of the supply, and are inconsistent with a 10 V gate.

Answer: B

The drain current in a JFET is controlled by the gate-source voltage.

The JFET is a voltage-controlled device. A reverse bias on the gate-source junction widens the depletion region into the channel, narrowing it and reducing the drain current. Shockley's equation gives the relation:

\[ I_D = I_{DSS}\left(1 - \frac{V_{GS}}{V_P}\right)^{2} \]

The gate is reverse biased, so gate current is almost zero and controls nothing. In saturation the drain voltage has little effect on the current. Source current is simply the drain current flowing out, a result rather than a control.